Patents by Inventor Maurizio Zuffada

Maurizio Zuffada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080170488
    Abstract: A method for non-destructive reading of a datum stored in a ferroelectric material in a stable state of polarization, the method including applying a read electrical quantity to the ferroelectric material having a value such as not to cause a variation in the stable state of polarization thereof, generating an output quantity indicative of a polarization charge variation occurring in the ferroelectric material during application of the read electrical quantity, and determining the value of the stored datum based on the output quantity. In particular, the polarization charge variation is given by a difference between a first value assumed by the polarization charge in the stable state of the ferroelectric material and a second value assumed by the polarization charge during application of the read electrical quantity.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 17, 2008
    Applicant: STMicroelectronics S.r.l.
    Inventors: Maurizio Zuffada, Michele Fedeli, Guido Gabriele Albasini, Matteo Rossi
  • Patent number: 6842062
    Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: January 11, 2005
    Assignees: STMicroelectronics S.r.l., International Business Machines Corporation
    Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
  • Patent number: 6777998
    Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: August 17, 2004
    Assignees: STMicroelectronics S.r.l., International Business Machines Corporation
    Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
  • Publication number: 20030058024
    Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.
    Type: Application
    Filed: August 9, 2002
    Publication date: March 27, 2003
    Applicant: STMicroelectronics S.r.I.
    Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
  • Publication number: 20030058025
    Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.
    Type: Application
    Filed: August 9, 2002
    Publication date: March 27, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Maurizio Zuffada, Giorgio Betti, Francesco Chrappan Soldavini, Martin Aureliano Hassner
  • Patent number: 6078462
    Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: June 20, 2000
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Maurizio Zuffada, Paolo Gadducci, David Moloney, Valerio Pisati
  • Patent number: 6067198
    Abstract: A device comprises a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter, and two distinct and parallel sampling channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two sampling channels each comprise an analog-to-digital converter and a Viterbi detector arranged in series and operating according to sampling sequences that alternate with one another.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: May 23, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maurizio Zuffada, Paolo Gadducci, David Moloney, Roberto Alini
  • Patent number: 5526486
    Abstract: A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: June 11, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: David Moloney, Maurizio Zuffada, Gianfranco Vai, Fabrizio Sacchi
  • Patent number: 5495201
    Abstract: A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: February 27, 1996
    Assignee: SGS Thomson Microelectronics, S.r.l.
    Inventors: Roberto Alini, Maurizio Zuffada, David Moloney, Silvano Gornati
  • Patent number: 5408436
    Abstract: The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: April 18, 1995
    Assignee: SGS-Thomson Micorelectronics S.r.l.
    Inventors: David Moloney, Gianfranco Vai, Maurizio Zuffada, Giorgio Betti, Fabrizio Sacchi
  • Patent number: 5365193
    Abstract: A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: November 15, 1994
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Maurizio Zuffada, Gianfranco Vai, Marco Gregori, David Moloney, Giorgio Betti
  • Patent number: 5352944
    Abstract: A circuit particularly useful in AGC systems, produces an output current which is proportional to the difference between a signal voltage and a reference voltage which is practically independent of temperature. By being a function of a ratio among actual values of integrated resistances and of a ratio among substantially temperature-stable voltages. The effects of temperature dependent value of integrated resistances and of temperature-dependent electrical characteristics of integrated semiconductor devices are compensated in order to produce the desired temperature-independent output current which may usefully be utilized for implementing an automatic gain control.
    Type: Grant
    Filed: April 1, 1993
    Date of Patent: October 4, 1994
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Fabrizio Sacchi, Maurizio Zuffada, Gianfranco Vai, David Moloney
  • Patent number: 5263186
    Abstract: In a dynamic automatic loop for control of the overall gain of an input circuit of a superheterodyne receiver, the response time of the HF-AGC circuit of the TUNER, in response to the action of the TUNER DELAY circuit activated by the IF-AGC in the case of autonomously uncontrollable abrupt increases in the level of the antenna signal from the same HF-AGC of the TUNER, is markedly reduced using an additional TUNER DELAY PLUS circuit able to absorb for a determined interval of time, a discharge current from the storage capacitor the control voltage of the HF-AGC in addition to the discharge current absorbed by the existing TUNER DELAY circuit. The relevant intensity of this additional discharge current and its duration are optimized by way of suitable circuital arrangements in the design of said TUNER DELAY PLUS circuit. The response time is reduced without modifying the time constant of the HF-AGC, which cannot be freely reduced because of inter- and cross-modulation problems.
    Type: Grant
    Filed: January 15, 1991
    Date of Patent: November 16, 1993
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Silvano Gornati, Giorgio Betti, Fabrizio Sacchi, Gianfranco Vai, Maurizio Zuffada
  • Patent number: 5231362
    Abstract: A circuit device for phasing an oscillator, which comprises a multivibrator having a transistor pair with the emitters coupled through a capacitor, comprises a normally open electronic switch controlled by a drive signal to close and inhibit the oscillator. This switch connects a voltage divider to the base of a transistor connected to one of the emitters to interrupt the loop positive feedback of the oscillator upon the voltage across the capacitor reaching a predetermined value.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: July 27, 1993
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Gianfranco Vai, Maurizio Zuffada, Fabrizio Sacchi, David Moloney, Giorgio Betti
  • Patent number: 5200653
    Abstract: The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: April 6, 1993
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: David Moloney, Gianfranco Vai, Maurizio Zuffada, Giorgio Betti
  • Patent number: 5187452
    Abstract: A control circuit for an oscillator comprising a multivibrator with transistors having their emitters connected in common and being supplied corresponding currents on respective legs, comprises a circuit structure adapted to produce on output terminals, on the one side, a current which is proportional to a reference current according to a predetermined parameter, and on the other side, a second current in turn correlated to the reference current as a function of said parameter, thereby to modify the oscillator duty cycle for a given operating frequency.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: February 16, 1993
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Gianfranco Vai, Maurizio Zuffada, Fabrizio Sacchi, David Moloney, Giorgio Betti
  • Patent number: 5142204
    Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit incorporating,a frequency meter being input and analog synchronization signal.a phase comparator having two inputs and in turn receiving said synchronization signal on one input,a voltage-controlled oscillator adapted to output a signal whose frequency is depending on said voltage and operatively linked to an output of said phase comparator, anda counter connected with its input, on the one side, to the oscillator output, and on the other side, to the meter output, said counter having an output connected to the other input of the phase comparator also forming the integrated circuit output.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: August 25, 1992
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Silvano Gornati, Mauro Merlo, Maurizio Zuffada, Loic Lietar
  • Patent number: 5134481
    Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: July 28, 1992
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Silvano Gornati, Giorgio Betti, Fabrizio Sacchi, Gianfranco Vai, Maurizio Zuffada
  • Patent number: RE35588
    Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit incorporating,a frequency meter being input and analog synchronization signal.a phase comparator having two inputs and in turn receiving said synchronization signal on one input,a voltage-controlled oscillator adapted to output a signal whose frequency is depending on said voltage and operatively linked to an output of said phase comparator, anda counter connected with its input, on the one side, to the oscillator output, and on the other side, to the meter output, said counter having an output connected to the other input of the phase comparator also forming the integrated circuit output.
    Type: Grant
    Filed: August 25, 1994
    Date of Patent: August 19, 1997
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Silvano Gornati, Mauro Merlo, Maurizio Zuffada, Loic Lietar
  • Patent number: RE36508
    Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: January 18, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Silvano Gornati, Giorgio Betti, Fabrizio Sacchi, Gianfranco Vai, Maurizio Zuffada