Abstract: Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.

Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.

Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.

Abstract: Mechanisms or techniques for improving operations such as program or erase operations that are intended to set a state of one or more multi-level memory cells (MLC) to a selected or designated state. For example, a first voltage pulse can be applied to an MLC that is intended to set the MLC to a desired state. Thereafter, a sensing pulse can be applied to the MLC, and one or more suitable electrical characteristic (EC) such as resistance can be measured and reported. This measured EC can then be compared to thresholds that define the range of acceptable values for the EC in order for the MLC to be deemed to be in the selected state. If the measured EC is not within the suitable range threshold, then one or more additional voltage pulses can be applied in order to properly set the MLC to the designated state and these additional voltages pulses can have different characteristics than the first voltage pulse.

Abstract: In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.

Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Abstract: Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.

Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Abstract: Providing for improved cell longevity for two-terminal memory devices is described herein. By way of example, wear leveling and management of array operations is provided to reduce an average number of set or reset cycles employed for programming new data to a two-terminal memory device. Reduction in set and reset cycles can facilitate reduced wear over time, increasing longevity of the memory device and enabling larger numbers of lifetime array operations. Wear leveling can comprise comparing existing data stored within a target set of memory cells, to new data to be written to the target cells, and changing only cells having different values between the existing and new data. In some examples, new data can be inverted to reduce a number of program or erase pulses required to program the new data over the existing data, among other examples of disclosed wear leveling.

Abstract: A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the smart-card portion, and a memory device in communication with the controller. The memory device can be separate from the smart-card portion and can store one or more smart-card applications.

Abstract: Two-terminal memory can be configured as multi-level cell (MLC) memory in which a single memory cell can represent multiple bits of information. Unlike certain other memories that are subject to disturb errors, for the disclosed two-terminal memory, these multiple bits can store information that is included in the same logical page of memory, which can be advantageous. However, performing error-code correction (ECC) operations on multiple bits of data from the same MLC can result in additional stress on an ECC engine because if a MLC fails, all bits of that cell are likely to be bad. Splitting the multiple bits of a MLC in connection with encoding or decoding can average the errors from bad cells across multiple ECC codewords, thereby providing better coverage with the same ECC or reducing the overhead associated with ECC coverage.

Abstract: A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. The smart-card device stores critical security parameters that are provided to the controller to protect access to some or all of the partitions of the memory device. A host connected to the controller issues commands, and the controller analyzes the commands and responds to them in various ways depending upon the nature of the command. In particular, depending upon the nature of the command, the controller may either pass the command to the smart-card device, or ignore the command either indefinitely or until a predetermined event has occurred.

Abstract: A two-terminal memory array can be configured to address a single memory cell. A two-terminal memory array can further be configured to mitigate disturb errors associated with other types of memory (e.g., non-two-terminal memory such as NAND flash memory). Mitigation of disturb errors can allow re-writes and/or overwrites of data stored by the cells without a prior erase operation. In this regard, errors in the data read from a memory array can be corrected by error-correction code (ECC) and associated corrected data can be written back to the memory cells that store the portions of data determined by the ECC to be erroneous data and/or incorrect or bad data.

Abstract: An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.

Abstract: A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data. The memory device may also be used to store data or instructions for use by the smart-card device. The controller includes a security engine that uses critical security parameters stored in, and received from, the smart-card device. The critical security parameters may be sent to the controller in a manner that protects them from being discovered. The critical security parameters may be encryption and/or decryption keys that may encrypt data written to the memory device and/or decrypt data read from the memory device, respectively. Data and instructions used by the smart-card device may therefore stored in the memory device in encrypted form.

Abstract: A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.