Abstract: Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller, where the controller operates in accordance with the device firmware. The controller determines whether or not the device firmware can be updated with new firmware at least partially based on whether or not the new firmware meets a criterion related to a configuration profile of the device firmware.

Abstract: Flash geometry information of the solid state disk (SSD) is maintained as is a logically-addressable SSD (laSSD) geometry information of the SSD. Based on the flash geometry and the laSSD geometry, virtual super blocks are configured by dynamically binding logical SSD logical block addresses (SLBAs) of a virtual super block with a physical super block within the laSSD. A virtual super block is made of a number of virtual blocks and each virtual block made of a number of virtual pages. Each of the virtual blocks corresponds to a physical block of a physical super block within the laSSD such that the virtual pages of the virtual block correspond to like physical pages of a corresponding physical block. Host logical block addresses (LBAs) are assigned to laSSD LBAs (SLBAs), which identify the virtual super blocks used for striping across physical super blocks.

Abstract: In accordance with various embodiments of the invention, the storage processor 10, rather than the storage pool 26, determines locations within the storage pool 26 into which data from the host 12 is to be stored by controlling striping across the SSDs of the storage pool 26 thereby increasing performance of the overall system, i.e. storage system 10, storage pool 26 and host 12. Performance improvement is realized over that of prior art systems because the storage system 10 has a global view of data traffic of the overall system and is aware of what is going on with the overall system as opposed to the SSDs of the storage pool 26, which have comparatively limited view. In accordance with a method and apparatus of the invention, an exemplary manner in which the storage system 10 is capable of controlling addressing of the SSDs of the storage pool 26 is by maintaining geometry information of the SSDs in the memory 20 and maintaining virtual super blocks associated with the SSDs.

Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.

Abstract: A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. The smart-card device stores critical security parameters that are provided to the controller to protect access to some or all of the partitions of the memory device. A host connected to the controller issues commands, and the controller analyzes the commands and responds to them in various ways depending upon the nature of the command. In particular, depending upon the nature of the command, the controller may either pass the command to the smart-card device, or ignore the command either indefinitely or until a predetermined event has occurred.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.

Abstract: A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.

Abstract: In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. The smart-card device stores critical security parameters that are provided to the controller to protect access to some or all of the partitions of the memory device. A host connected to the controller issues commands, and the controller analyzes the commands and responds to them in various ways depending upon the nature of the command. In particular, depending upon the nature of the command, the controller may either pass the command to the smart-card device, or ignore the command either indefinitely or until a predetermined event has occurred.

Abstract: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.

Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.

Abstract: A storage system includes a storage processor coupled to solid state disks (SSDs) and a host, the SSDs are identified by SSD logical block addresses (SLBAs). The storage processor receives a command from the host to write data to the SSDs and further receives a location within the SSDs to write the data, the location being referred to as a host LBA. The storage processor includes a central processor unit (CPU) subsystem and maintains unassigned SLBAs of a corresponding SSD. The CPU subsystem upon receiving the command to write data, generates sub-commands based on a range of host LBAs derived from the received command and further based on a granularity. At least one of the host LBAs is non-sequential relative to the remaining host LBAs. The CPU subsystem assigns the sub-commands to unassigned SLBAs by assigning each sub-command to a distinct SSD of a stripe, the host LBAs being decoupled from the SLBAs.

Abstract: A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may he used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may he accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.

Abstract: A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array.

Abstract: A method of managing redundant array of independent disk (RAID) groups in a storage system includes determining wear of each of the plurality of RAID groups, computing the weight for each of RAID groups based on the wear, and striping data across at least one of the RAID groups based on the weight of each of the RAID groups.

Abstract: A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation.