Patents by Inventor Mehrdad Mofidi
Mehrdad Mofidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923341Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: September 3, 2021Date of Patent: March 5, 2024Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20230260969Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Patent number: 11670620Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: January 29, 2020Date of Patent: June 6, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20230131169Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Patent number: 11580038Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: GrantFiled: February 5, 2021Date of Patent: February 14, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Publication number: 20210398949Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20210248094Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Inventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Publication number: 20200243486Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: January 29, 2020Publication date: July 30, 2020Applicant: Sunrise Memory CorporationInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20120167100Abstract: An external controller has greater control over control circuitry on a memory die in a non-volatile storage system. The external controller can issue a manual suspend command on a communication path which is constantly monitored by the control circuitry. In response, the control circuitry suspends a task immediately, with essentially no delay, or at a next acceptable point in the task. The external controller similarly has the ability to issue a manual resume command, which can be provided on the communication path when that path has a ready status. The control circuitry can also automatically suspend and resume a task. The external controller can cause a task to be suspended by issuing an illegal read command. The external controller can cause a suspended program task to be aborted by issuing a new program command.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Yan Li, Alon Marcu, Cynthia Hsu, Grishma Shah, Cuong Trinh, Mehrdad Mofidi
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Patent number: 7890694Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: GrantFiled: May 20, 2009Date of Patent: February 15, 2011Assignee: SanDisk CorporationInventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Publication number: 20090228644Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: ApplicationFiled: May 20, 2009Publication date: September 10, 2009Inventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Patent number: 7532514Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: GrantFiled: August 31, 2007Date of Patent: May 12, 2009Assignee: Sandisk CorporationInventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid
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Patent number: 7447093Abstract: Method for controlling voltage in a non-volatile memory system is provided. The method includes selecting a first input value for a voltage generator system operating in one of a plurality of modes, the first input value controlling a temperature dependent component of a voltage applied to a memory cell; and selecting a second input value for the voltage generator system operating in one of the plurality of modes, the second input value controlling a temperature independent component of the voltage applied to the memory cell. The temperature dependent component of the voltage applied to the memory cell and the temperature independent component of the voltage applied to the memory cell are controlled independently in response to the first input value and the second input value.Type: GrantFiled: December 29, 2006Date of Patent: November 4, 2008Assignee: SanDisk CorporationInventors: Jun Li, Prajit Nandi, Mehrdad Mofidi
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Patent number: 7403434Abstract: System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell of the non-volatile memory system. For one of the plurality of modes, a first input value is selected for controlling a temperature dependent component of the voltage and a second input value is selected for controlling a temperature independent component of the voltage. The temperature dependent component of the voltage and the temperature independent component of the voltage are controlled independently in response to the first input value and the second input value.Type: GrantFiled: December 29, 2006Date of Patent: July 22, 2008Assignee: SanDisk CorporationInventors: Jun Li, Prajit Nandi, Mehrdad Mofidi
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Publication number: 20080158947Abstract: System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell of the non-volatile memory system. For one of the plurality of modes, a first input value is selected for controlling a temperature dependent component of the voltage and a second input value is selected for controlling a temperature independent component of the voltage. The temperature dependent component of the voltage and the temperature independent component of the voltage are controlled independently in response to the first input value and the second input value.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Jun Li, Prajit Nandi, Mehrdad Mofidi
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Publication number: 20080159000Abstract: Method for controlling voltage in a non-volatile memory system is provided. The method includes selecting a first input value for a voltage generator system operating in one of a plurality of modes, the first input value controlling a temperature dependent component of a voltage applied to a memory cell; and selecting a second input value for the voltage generator system operating in one of the plurality of modes, the second input value controlling a temperature independent component of the voltage applied to the memory cell. The temperature dependent component of the voltage applied to the memory cell and the temperature independent component of the voltage applied to the memory cell are controlled independently in response to the first input value and the second input value.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Jun Li, Prajit Nandi, Mehrdad Mofidi
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Publication number: 20070297234Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: ApplicationFiled: August 31, 2007Publication date: December 27, 2007Inventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid
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Patent number: 7269069Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: GrantFiled: June 2, 2006Date of Patent: September 11, 2007Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid
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Patent number: 7215574Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: GrantFiled: October 13, 2005Date of Patent: May 8, 2007Assignee: Sandisk CorporationInventors: Shahzad Khalid, Yan Li, Raul-Adrian Cernea, Mehrdad Mofidi
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Publication number: 20060227614Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: ApplicationFiled: June 2, 2006Publication date: October 12, 2006Inventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid