Patents by Inventor Mehrdad Mofidi
Mehrdad Mofidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7064980Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: GrantFiled: September 17, 2003Date of Patent: June 20, 2006Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid
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Publication number: 20060034121Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: ApplicationFiled: October 13, 2005Publication date: February 16, 2006Inventors: Shahzad Khalid, Yan Li, Raul-Adrian Cernea, Mehrdad Mofidi
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Patent number: 6956770Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: GrantFiled: September 17, 2003Date of Patent: October 18, 2005Assignee: SanDisk CorporationInventors: Shahzad Khalid, Yan Li, Raul-Adrian Cernea, Mehrdad Mofidi
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Publication number: 20050057965Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: ApplicationFiled: September 17, 2003Publication date: March 17, 2005Inventors: Raul-Adrian Cernea, Yan Li, Mehrdad Mofidi, Shahzad Khalid
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Publication number: 20050057967Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.Type: ApplicationFiled: September 17, 2003Publication date: March 17, 2005Inventors: Shahzad Khalid, Yan Li, Raul-Adrian Cernea, Mehrdad Mofidi
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Patent number: 6829673Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: GrantFiled: November 1, 2002Date of Patent: December 7, 2004Assignee: SanDisk CorporationInventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Publication number: 20030200380Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: ApplicationFiled: May 27, 2003Publication date: October 23, 2003Inventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Patent number: 6542956Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: GrantFiled: August 21, 2000Date of Patent: April 1, 2003Assignee: SanDisk CorporationInventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Publication number: 20030061437Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: ApplicationFiled: November 1, 2002Publication date: March 27, 2003Inventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Patent number: 6157983Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: GrantFiled: January 6, 1999Date of Patent: December 5, 2000Assignee: SanDisk CorporationInventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Patent number: 6069039Abstract: An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasing selected addressable data sectors of the EEPROM device. Included in the erase circuitry are a plurality of erase voltage generating circuits, a corresponding plurality of switching circuitry, and switch control circuitry shared by the plurality of switching circuitry for controlling the selectable coupling of erase voltages generated by the erase voltage generating circuits to corresponding data sectors of the EEPROM device.Type: GrantFiled: April 21, 1998Date of Patent: May 30, 2000Assignee: SanDisk CorporationInventors: Douglas J. Lee, Sanjay Mehrotra, Mehrdad Mofidi, Daniel C. Guterman
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Patent number: 5890192Abstract: An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.Type: GrantFiled: November 5, 1996Date of Patent: March 30, 1999Assignee: SanDisk CorporationInventors: Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Patent number: 5798968Abstract: An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasing selected addressable data sectors of the EEPROM device. Included in the erase circuitry are a plurality of erase voltage generating circuits, a corresponding plurality of switching circuitry, and switch control circuitry shared by the plurality of switching circuitry for controlling the selectable coupling of erase voltages generated by the erase voltage generating circuits to corresponding data sectors of the EEPROM device.Type: GrantFiled: September 24, 1996Date of Patent: August 25, 1998Assignee: SanDisk CorporationInventors: Douglas J. Lee, Sanjay Mehrotra, Mehrdad Mofidi, Daniel C. Guterman
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Patent number: 5693570Abstract: A process for manufacturing a flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: November 18, 1996Date of Patent: December 2, 1997Assignee: SanDisk CorporationInventors: Raul-Ardian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5621685Abstract: An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: June 7, 1995Date of Patent: April 15, 1997Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5596532Abstract: An EEPROM system operative within a continuous source voltage range includes a controller having a processor and a memory, and an EEPROM module connected to the controller and including a plurality of EEPROM chips. A representative one of the EEPROM chips includes a comparator, a programmable voltage generator, and a regulated charge pump circuit. The comparator compares a source voltage provided to the EEPROM system against one or more reference voltages indicative of subranges within the operative source voltage range, to generate one or more control signals indicative of the subrange within which the source voltage resides. The regulated charge pump circuit generates from the source voltage, a regulated high voltage output which is substantially unaffected by changes in the source voltage. Included in the regulated charge pump circuit are a feedback circuit, and an open loop gain adjustment circuit which is responsive to the the one or more control signals generated by the comparator.Type: GrantFiled: October 18, 1995Date of Patent: January 21, 1997Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5592420Abstract: An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: June 7, 1995Date of Patent: January 7, 1997Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5568424Abstract: An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: June 7, 1995Date of Patent: October 22, 1996Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5563825Abstract: An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: June 7, 1995Date of Patent: October 8, 1996Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra
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Patent number: 5508971Abstract: An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp.Type: GrantFiled: October 17, 1994Date of Patent: April 16, 1996Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra