Abstract: A communication system includes a first communication system and a second communication terminal. The first communication terminal generates a first shared key, and the second communication terminal generates a second shared key. During an exchange operation, the first communication terminal stores the second shared key of the second communication terminal, and the second communication terminal stores the first shared key of the first communication terminal. During a challenge operation, the first communication terminal sends a challenge string to the second communication terminal, the second communication terminal generates a response string by performing reversible encryption operations to the challenge string with the first shared key and the second shared key, the second communication terminal sends the response string to the first communication terminal, and the first communication terminal verifies the response string.

Abstract: A random number generator includes a counting value generator, an address generator, a static entropy source and a processing circuit. The counting value generator generates a first random number. The address generator generates an address signal. The static entropy source is connected with the address generator to receive the address signal and generates a second random number. The processing circuit is connected with the static entropy source and the counting value generator to receive the first random number and the second random number. After the first random number and the second random number are processed by the processing circuit, the processing circuit generates an output random number.

Abstract: A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.

Abstract: A security system with entropy bits includes a physically unclonable function circuit, and a security key generator. The physically unclonable function circuit provides a plurality of entropy bit strings. The security key generator generates a security key by manipulating a manipulation bit string derived from the plurality of entropy bit strings according to an operation entropy bit string. Each bit of the operation entropy bit string is used to determine whether to perform a corresponding operation to the manipulation bit string.

Abstract: A communication system includes a first communication system and a second communication terminal. The first communication terminal generates a first shared key, and the second communication terminal generates a second shared key. During an exchange operation, the first communication terminal stores the second shared key of the second communication terminal, and the second communication terminal stores the first shared key of the first communication terminal. During a challenge operation, the first communication terminal sends a challenge string to the second communication terminal, the second communication terminal generates a response string by performing reversible encryption operations to the challenge string with the first shared key and the second shared key, the second communication terminal sends the response string to the first communication terminal, and the first communication terminal verifies the response string.

Abstract: A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.

Abstract: An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

Abstract: The communication system includes a communication buffer and a communication terminal. The communication buffer includes a physical unclonable function (PUF) device, and the communication buffer provides a security key generated by the PUF device. The communication terminal is coupled to the communication buffer, and transmits a mapping request to the communication buffer to ask for the security key. The communication terminal manipulates the transmission data with the security key to generate the encrypted data, and transmits the encrypted data to the communication buffer. The communication buffer further restores the transmission data from the encrypted data according to the security key.

Abstract: A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.

Abstract: A security system includes a physical unclonable function circuit, a write-in protection circuit, a memory, and a readout decryption circuit. The physical unclonable function circuit provides a plurality of random bit strings. The write-in protection circuit receives a write-in address and original data, and includes an address scrambling unit. The address scrambling unit generates a scrambled address by scrambling a write-in address according to a random bit string provided by the physical unclonable function circuit. The memory stores the storage data corresponding to the original data according to the scrambled address. The readout decryption circuit reads out the storage data from the memory according to the write-in address to derive the original data.

Abstract: A security system with entropy bits includes a physically unclonable function circuit, and a security key generator. The physically unclonable function circuit provides a plurality of entropy bit strings. The security key generator generates a security key by manipulating a manipulation bit string derived from the plurality of entropy bit strings according to an operation entropy bit string. Each bit of the operation entropy bit string is used to determine whether to perform a corresponding operation to the manipulation bit string.

Abstract: A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.

Abstract: An antifuse physically unclonable function (PUF) unit includes a first sub-antifuse cell, a second sub-antifuse cell, a connection circuit, a first copying circuit and a first reading circuit. The first sub-antifuse cell includes a first antifuse transistor. The second sub-antifuse cell includes a second antifuse transistor. The connection circuit is connected between a source/drain terminal of the first antifuse transistor and a source/drain terminal of the second antifuse transistor. The first copying circuit is connected with the first sub-antifuse cell, and includes a third antifuse transistor. The first reading circuit is connected with the first copying circuit. Moreover, the first reading circuit generates a random code according to a state of the third antifuse transistor.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

Abstract: An antifuse physically unclonable function (PUF) unit includes a first sub-antifuse cell, a second sub-antifuse cell, a connection circuit, a first copying circuit and a first reading circuit. The first sub-antifuse cell includes a first antifuse transistor. The second sub-antifuse cell includes a second antifuse transistor. The connection circuit is connected between a source/drain terminal of the first antifuse transistor and a source/drain terminal of the second antifuse transistor. The first copying circuit is connected with the first sub-antifuse cell, and includes a third antifuse transistor. The first reading circuit is connected with the first copying circuit. Moreover, the first reading circuit generates a random code according to a state of the third antifuse transistor.

Abstract: A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

Abstract: A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.