Patents by Inventor Meng-Yi Wu
Meng-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7888194Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.Type: GrantFiled: March 5, 2007Date of Patent: February 15, 2011Assignee: United Microelectronics Corp.Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
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Patent number: 7875520Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.Type: GrantFiled: March 27, 2008Date of Patent: January 25, 2011Assignee: United Microelectronics Corp.Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
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Patent number: 7622344Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.Type: GrantFiled: July 17, 2007Date of Patent: November 24, 2009Assignee: United Microelectronics Corp.Inventors: Chia-Wen Liang, Cheng-Tung Huang, Shyh-Fann Ting, Chih-Chiang Wu, Shih-Chieh Hsu, Li-Shian Jeng, Kun-Hsien Lee, Meng-Yi Wu, Wen-Han Hung, Tzyy-Ming Cheng
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Publication number: 20090246922Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
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Publication number: 20090239347Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.Type: ApplicationFiled: May 20, 2009Publication date: September 24, 2009Applicant: United Microelectronics Corp.Inventors: SHYH-FANN TING, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
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Publication number: 20090224328Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.Type: ApplicationFiled: March 4, 2008Publication date: September 10, 2009Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Tzyy-Ming Cheng, Jing-Chang Wu, Tzer-Min Shen
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Publication number: 20090186475Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.Type: ApplicationFiled: January 21, 2008Publication date: July 23, 2009Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Shih-Chieh Hsu, Chih-Chiang Wu, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Wen-Han Hung, Yao-Chin Cheng, Chi-Sheng Tseng, Yu-Ming Lin, Shih-Jung Tu, Tzyy-Ming Cheng
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Publication number: 20090166625Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shyh-Fann Ting, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
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Publication number: 20090117701Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Inventors: Meng-Yi Wu, Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Chung-Min Shih, Yao-Chin Cheng, Tzyy-Ming Cheng
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Publication number: 20090023258Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Inventors: Chia-Wen Liang, Cheng-Tung Huang, Shyh-Fann Ting, Chih-Chiang Wu, Shih-Chieh Hsu, Li-Shian Jeng, Kun-Hsien Lee, Meng-Yi Wu, Wen-Han Hung, Tzyy-Ming Cheng
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Publication number: 20080242031Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
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Publication number: 20080237734Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Chung-Min Shih, Tzyy-Ming Cheng, Chia-Wen Liang
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Publication number: 20080220574Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.Type: ApplicationFiled: March 5, 2007Publication date: September 11, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
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Publication number: 20080206942Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.Type: ApplicationFiled: February 26, 2007Publication date: August 28, 2008Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
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Patent number: 6580641Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.Type: GrantFiled: October 31, 2002Date of Patent: June 17, 2003Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin Kin, Ching-Hsiang Hsu
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Publication number: 20030086296Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.Type: ApplicationFiled: October 31, 2002Publication date: May 8, 2003Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu
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Publication number: 20030068845Abstract: A method for manufacturing a flash device having a trench source line comprises providing a semiconductor substrate. A pad oxide is formed on a substrate, then forming a nitride layer on the pad oxide. The nitride layer and the pad oxide layer are patterned then etching the substrate to form a trench in the substrate. An ion implantation is performed to dope ions into the substrate under the trench to form the trench source line. Next, refilling material is refilled into the trench, followed by performing chemical mechanical polishing to remove a portion of the refilling material to the substrate. A gate dielectric layer, a first doped conductive layer, an inter conductive dielectric layer, a second conductive layer are formed. The first conductive layer, the second conductive layer and the inter conductive dielectric layer are etched to form gate structure. Subsequently, source and drain regions are formed by ion implantation and halo-doped region is formed under the drain regions by ion implantation.Type: ApplicationFiled: August 1, 2002Publication date: April 10, 2003Inventors: Fu-Yuan Chen, Ching-Hsiang Hsu, Ya-Chin King, Ching-Sung Yang, Hsiu-Fen Chou, Kung-Hong Lee, Meng-Yi Wu
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Patent number: 6518126Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.Type: GrantFiled: April 23, 2002Date of Patent: February 11, 2003Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu
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Publication number: 20020175394Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.Type: ApplicationFiled: April 23, 2002Publication date: November 28, 2002Inventors: Meng-Yi Wu, Kung-Hong Lee, Fu-Yuan Chen, Hsin-Fen Chou, Ching-Song Yang, Ya-Chin King, Ching-Hsiang Hsu