Patents by Inventor Mi Jin Park
Mi Jin Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190393168Abstract: A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.Type: ApplicationFiled: November 5, 2018Publication date: December 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi Jin PARK, Ji Eun PARK, Job HA
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Publication number: 20170365567Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads, the semiconductor chip includes a passivation layer having openings exposing at least portions of the connection pads, the redistribution layer of the second interconnection member is connected to the connection pad through a via, a metal layer is disposed between the connection pad and the via, and the metal layer covers at least a portion of the connection pad.Type: ApplicationFiled: December 5, 2016Publication date: December 21, 2017Inventors: Yun Bog KIM, Mi Jin PARK, Yeon Seop YU, Shang Hoon SEO
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Publication number: 20160198568Abstract: A printed circuit board includes a first insulating layer including a first circuit pattern, a second insulating layer including a second circuit pattern, and a dummy pattern disposed in the first insulating layer and the second insulating layer, in which the first and second insulating layers are made of different materials. An electronic component module includes a printed circuit board and an electronic component mounted on the printed circuit board.Type: ApplicationFiled: January 4, 2016Publication date: July 7, 2016Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin PARK, Kyoung Moo HARR, Seung Wan SHIN
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Patent number: 9253880Abstract: Disclosed herein is a printed circuit board, including: a core layer; and a plurality of circuit layers stacked on the core layer, wherein one of the circuit layers includes a mesh pattern and a solid pattern, and another of the circuit layers include a first signal pattern opposite to the mesh pattern and a second signal pattern opposite to the solid pattern, the second signal pattern having a high-speed signal line with a higher speed, as compared with the second signal pattern.Type: GrantFiled: November 29, 2012Date of Patent: February 2, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin Park, Romero Christian, Seung Wook Park
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Patent number: 9236339Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t? formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness ? from a top of the circuit pattern, wherein T?t?+? is satisfied, T represents a sum of the thicknesses t and t? and t? is a thickness of a portion of the circuit pattern formed on the via plug.Type: GrantFiled: May 31, 2013Date of Patent: January 12, 2016Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Christian Romero, Chang Bae Lee, Mi Jin Park
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Patent number: 9204533Abstract: Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.Type: GrantFiled: October 30, 2012Date of Patent: December 1, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Romero Christian, Seung Wook Park, Young Do Kweon, Mi Jin Park
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Patent number: 9095068Abstract: Disclosed herein is a circuit board including: a base substrate including a via for power and a via pad for power connected to the via for power; and an insulating layer formed on the base substrate and including a dummy pattern formed in a region facing the via pad for power.Type: GrantFiled: December 11, 2012Date of Patent: July 28, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Chang Bae Lee, Christian Romero, Mi Jin Park
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Patent number: 8987888Abstract: Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.Type: GrantFiled: February 8, 2012Date of Patent: March 24, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin Park, Christian Romero, Seung Wook Park
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Publication number: 20150055312Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.Type: ApplicationFiled: April 11, 2014Publication date: February 26, 2015Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Jeong Ho LEE, Mi Jin PARK, Chang Bae LEE, Young Do KWEON
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Publication number: 20140338955Abstract: Disclosed herein is a printed circuit board. According to a preferred embodiment of the present invention, the printed circuit board, includes: a base board; an upper build-up layer which is formed on the base board and includes an upper insulating layer and an upper circuit layer having at least one layer; and a lower build-up layer which is formed beneath the base board, has a different thickness from the upper build-up layer, and includes a lower insulating layer and a lower circuit layer having at least one layer.Type: ApplicationFiled: December 2, 2013Publication date: November 20, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Mi Jin Park, Jeong Ho Lee, Young Nam Hwang, Young Do Kweon
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Patent number: 8830689Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.Type: GrantFiled: September 15, 2011Date of Patent: September 9, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Gu Kim, Mi Jin Park, Young Ho Kim, Seung Wook Park, Hee Kon Lee, Young Do Kweon
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Publication number: 20140061864Abstract: Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device.Type: ApplicationFiled: March 14, 2013Publication date: March 6, 2014Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Gul HYUN, Mi Jin Park, Kyung Seob Oh
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Publication number: 20130320561Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t? formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness ? from a top of the circuit pattern, wherein T?t?+? is satisfied, T represents a sum of the thicknesses t and t? and t? is a thickness of a portion of the circuit pattern formed on the via plug.Type: ApplicationFiled: May 31, 2013Publication date: December 5, 2013Inventors: Seung Wook PARK, Romero CHRISTIAN, Chang Bae LEE, Mi Jin PARK
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Patent number: 8581394Abstract: Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure.Type: GrantFiled: October 5, 2010Date of Patent: November 12, 2013Assignee: Samsung Electro-Mechanics Co., LtdInventors: Seung Wook Park, Young Do Kweon, Mi Jin Park
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Patent number: 8582314Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.Type: GrantFiled: August 10, 2010Date of Patent: November 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Seung Wan Shin, Mi Jin Park, Kyung Seob Oh
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Publication number: 20130168143Abstract: Disclosed herein is a circuit board including: an insulating material; a build-up layer formed on one surface of the insulating material, and including at least one circuit layer and at least one insulating layer; and a metal layer formed on the other surface of the insulating material and electrically disconnected from the circuit layer.Type: ApplicationFiled: April 24, 2012Publication date: July 4, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Mi Jin Park, Christian Romero, Young Do Kweon
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Publication number: 20130127053Abstract: Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.Type: ApplicationFiled: February 8, 2012Publication date: May 23, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Mi Jin PARK, Christian ROMERO, Seung Wook PARK
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Publication number: 20130075144Abstract: Disclosed herein are a package substrate and a method for manufacturing the same. According to an exemplary embodiment, there is provided a package substrate with a mesh pattern, including: a plurality of bonding pads forming sections connected with the outside; an insulating layer formed below the plurality of bonding pads; and a metallic layer placed below the insulating layer and having the mesh pattern in at least a partial area thereof and capacitance is provided by a combination of the mesh pattern and the insulating layer that infiltrates into a space for the mesh pattern. Further, there is provided a method for manufacturing the package substrate with the mesh pattern.Type: ApplicationFiled: September 7, 2012Publication date: March 28, 2013Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin PARK, Seung Wook PARK, Romero CHRISTIAN
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Patent number: 8373537Abstract: There are provided a resistor and a method of fabricating the same. The resistor includes: a substrate; a lower resistant material layer formed on the upper portion of the substrate; an insulating layer to be stacked on the upper portion of the lower resistant material layer; an upper resistant material layer to be stacked on the upper portion of the insulating layer; and two penetration parts vertically penetrating through the insulating layer, wherein the penetration part is filled with a resistant material having the same component as that of the lower resistant material layer and the upper resistant material layer to electrically connect the upper resistant material layer to the lower resistant material layer.Type: GrantFiled: September 28, 2010Date of Patent: February 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin Park, Young Do Kweon, Jin Gu Kim
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Publication number: 20110309501Abstract: Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure.Type: ApplicationFiled: October 5, 2010Publication date: December 22, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Young Do Kweon, Mi Jin Park