Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.

Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.

Abstract: Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially the filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A method of encapsulating a circuit assembly including a chip; a substrate; at least one solder joint which spans between the chip and the substrate forming an electrically conductive connection between the chip and the substrate by applying an encapsulant adjacent the solder joint, wherein the encapsulant comprises a thermoplastic polymer formed by ring opening polymerization of a cyclic oligomer.

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract: Plastic ball grid array (PBGA) packages comprised of organic carriers on which are mounted and encapsulated semiconductor chips, providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A electronic package is constituted of a compliant multi-layered circuit board or printed circuit board package, particularly for use in ball grid array (BGA) applications wherein two or possibly greater numbers of naturally spaced sub-composites are equipped with electronic circuitry which is interconnected through the intermediary of conductive adhesives. Pursuant to a method of producing, no other mechanical connection is provided intermediate these spaced sub-composites except, possibly, along the periphery of the structure thereof, where a molded plastic seal may be provided in order to form a protection against the ingress environmental or external influences. The unfilled void, space or interspatial volume which is present between the spaced sub-composite facilitates the deformation in shear of the conductive adhesive interconnections, such as epoxy resins or the like, with extremely little constraint of the various components.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.

Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.

Abstract: Reworkable thermally conductive adhesive composition comprising a cured reaction product from a diepoxide wherein the epoxy groups are connected through an acyclic acetal moiety, a cyclic anhydride and a thermally conductive filler are provided and used to bond semiconductive devices to a chip carrier or heat spreader.

Abstract: A electronic package is constituted of a compliant multi-layered circuit board or printed circuit board package, particularly for use in ball grid array (BGA) applications wherein two or possibly greater numbers of naturally spaced sub-composites are equipped with electronic circuitry which is interconnected through the intermediary of conductive adhesives. Pursuant to a method of producing, no other mechanical connection is provided intermediate these spaced sub-composites except, possibly, along the periphery of the structure thereof, where a molded plastic seal may be provided in order to form a protection against the ingress environmental or external influences. The unfilled void, space or interspatial volume which is present between the spaced sub-composite facilitates the deformation in shear of the conductive adhesive interconnections, such as epoxy resins or the like, with extremely little constraint of the various components.

Abstract: Plastic ball grid array (PBGA) packages comprised of organic carriers on which are mounted and encapsulated semiconductor chips, providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A chip package includes a die having an active surface and an inactive surface. An adhesive is formed on the inactive surface where the adhesive has a low Young's modulus of elasticity. The low Young's modulus of elasticity may be 10,000 psi or less; 1,000 psi or less; or, preferably, about 1,000 psi. Further, the adhesive may include a thermal conducting material. A protective plate is coupled to the inactive surface using the adhesive and a chip carrier is coupled to the active surface of the die.

Abstract: The invention is an encapsulated circuit assembly including a chip; a substrate; at least one solder joint, wherein the solder joint spans between the chip and the substrate forming an electrically conductive connection between the chip and the substrate; and an encapsulant formed adjacent the solder joint, wherein the encapsulant comprises a hyperbranched polymer formed by the reaction of a monomer of the formula: (A)nRB, wherein A is a coupling group reactive with B, B is a coupling group reactive with A, n is greater than 1, and R is a group selected from the group consisting of an aromatic group, an aliphatic group, and mixtures thereof Also disclosed is a method of encapsulating a circuit assembly using the encapsulant of the invention.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.

Abstract: A method for joining electronic devices such as integrated circuits to vias in a substrate. A solder ball attached to an electronic device is joined to a contact pad of a via by a low melting temperature solder. An opening of a via is plugged to prevent wicking of the low melting temperature solder into the via hole. The opening of the via is plugged using a solder ball or a compressed length of a wire material.

Abstract: An aluminum or copper heat sink is attached to a ceramic cap or exposed semiconductor chip using an adhesive of silicone or flexible-epoxy adhesive. The aluminum may be coated by anodizing or chromate conversion or the copper may be coated with nickel or gold or chromium. Such structures are especially useful for flip chip attachment to flexible or rigid organic circuit boards or modules such as CQFP, CBGA, CCGA, CPGA, TBGA, PEGA, DCAM, MCM-L, and other chip carrier packages in which the back side of chips are connected directly to heat sinks. These adhesive materials withstand wet or dry thermal cycle tests of −65 to 1500° C. for 1,000 cycles and 85° C. and 85% relative humidity for 1000 hours while maintaining a tensile strenth of at least 500 psi. The adhesive contains materials having high thermal conductivity and a low coefficient of thermal expansion (CTE) in order to provide increased thermal performance.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.