Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract: A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.

Abstract: In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.

Abstract: System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.

Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.

Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Abstract: A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.

Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.

Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.

Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.

Abstract: Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A first data structure specifying that the first control information is associated with the first service type may be generated. A plurality of packets, including a multimedia stream according to the first service type, the first control information, and the first data structure, may be generated and transmitted. Second control information for configuring the audiovisual device to present a multimedia stream according to a second service type may be generated. The first data structure may be modified to include information about the second control information. A second plurality of packets, including the modified first data structure, the first control information, a multimedia stream according to the first service type, the second control information, and a multimedia stream according to the second service type, may be generated and transmitted.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.

Abstract: Bit efficient control information communication techniques. Control information for configuring an audiovisual device to present multimedia content may be generated. The control information may be organized according to a tree data structure having a plurality of nodes. The control information may include commands for navigating the nodes of the tree structure to locate data values stored at leaf nodes of the tree structure. Some commands may have associated data fields. Each command, and each data field, may include bit portions of uniform length. A designated bit of command bit portions may have a first value indicating that the bit portion is a command, while a designated bit of data field bit portions may have a second value indicating the bit portion is a data field. The second value may be different than the first value.