Patents by Inventor Michael B. Doerr
Michael B. Doerr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150026451Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: ApplicationFiled: October 2, 2014Publication date: January 22, 2015Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20140351551Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.Type: ApplicationFiled: May 23, 2014Publication date: November 27, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Publication number: 20140351557Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.Type: ApplicationFiled: August 5, 2014Publication date: November 27, 2014Inventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
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Patent number: 8880866Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: GrantFiled: October 14, 2011Date of Patent: November 4, 2014Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20140258974Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: John Mark Beardslee, Michael B. Doerr, Tommy K. Eng
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Patent number: 8832413Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.Type: GrantFiled: May 29, 2013Date of Patent: September 9, 2014Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
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Publication number: 20140247910Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.Type: ApplicationFiled: May 8, 2014Publication date: September 4, 2014Applicant: Coherent Logix IncorporatedInventors: David B. Drumm, James P. Golab, Jan D. Garmany, Kevin L. Shelby, Michael B. Doerr
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Patent number: 8826228Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.Type: GrantFiled: March 27, 2007Date of Patent: September 2, 2014Assignee: Coherent Logix, IncorporatedInventors: John Mark Beardslee, Michael B. Doerr, Tommy K. Eng
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Patent number: 8761318Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.Type: GrantFiled: January 4, 2013Date of Patent: June 24, 2014Assignee: Coherent Logix, IncorporatedInventors: David B. Drumm, James P. Golab, Jan D. Garmany, Kevin L. Shelby, Michael B. Doerr
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Publication number: 20140137082Abstract: System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.Type: ApplicationFiled: November 8, 2013Publication date: May 15, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Geoffrey N. Ellis, John Mark Beardslee, Michael B. Doerr, Ivan Aguayo, Brian A. Dalio
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Publication number: 20140075489Abstract: A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
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Patent number: 8650598Abstract: A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.Type: GrantFiled: November 30, 2012Date of Patent: February 11, 2014Assignee: Coherent Logix, IncorporatedInventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
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Patent number: 8644431Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.Type: GrantFiled: June 17, 2010Date of Patent: February 4, 2014Assignee: Coherent Logix, IncorporatedInventors: David B. Drumm, James P. Golab, Jan D. Garmany, Kevin L. Shelby, Michael B. Doerr
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Publication number: 20130343450Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficient and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.Type: ApplicationFiled: June 11, 2013Publication date: December 26, 2013Inventors: Michael B. Solka, Michael B. Doerr, Carl S. Dobbs, Michael W. Bruns
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Publication number: 20130263203Abstract: Bit efficient control information communication techniques. Control information for configuring an audiovisual device to present multimedia content may be generated. The control information may be organized according to a tree data structure having a plurality of nodes. The control information may include commands for navigating the nodes of the tree structure to locate data values stored at leaf nodes of the tree structure. Some commands may have associated data fields. Each command, and each data field, may include bit portions of uniform length. A designated bit of command bit portions may have a first value indicating that the bit portion is a command, while a designated bit of data field bit portions may have a second value indicating the bit portion is a data field. The second value may be different than the first value.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Inventors: Colleen J. McGinn, Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
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Publication number: 20130254515Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.Type: ApplicationFiled: May 29, 2013Publication date: September 26, 2013Applicant: Coherent Logix, IncorporatedInventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
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Patent number: 8489762Abstract: First control information, generated according to a first protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. A first data structure specifying that the first control information is of the first protocol version may be generated. A plurality of packets, including a multimedia stream, the first control information, and the first data structure, may be generated and transmitted. Second control information, generated according to a second protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. The first data structure may be modified to include information about the second control information. A second plurality of packets, including the modified first data structure, the first control information, a multimedia stream specified by the first control information, the second control information, and a multimedia stream specified by the second control information, may be generated.Type: GrantFiled: June 5, 2009Date of Patent: July 16, 2013Assignee: Coherent Logix, IncorporatedInventors: Colleen J. McGinn, Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
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Patent number: 8478964Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.Type: GrantFiled: December 30, 2011Date of Patent: July 2, 2013Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
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Publication number: 20130044105Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.Type: ApplicationFiled: August 20, 2012Publication date: February 21, 2013Inventors: Michael B. Doerr, Jan D. Garmany, Michael B. Solka, Martin A. Hunt
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Patent number: 8358705Abstract: A system and method for wirelessly transmitting audiovisual information. First audiovisual information may be encoded using a first error correction coding method. A plurality of packets may be generated, including the first audiovisual information, second audiovisual information, and control information. The second audiovisual information may not be encoded using the first error correction coding method, and the control information may indicate this. The plurality of packets may be wirelessly transmitted. The control information may be usable by a receiver to determine that the second audiovisual information is not encoded using the first error correction coding method, and may thereby determine that the second audiovisual information is a different service version than the first audiovisual information.Type: GrantFiled: May 29, 2009Date of Patent: January 22, 2013Assignee: Coherent Logix, IncorporatedInventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr