Patents by Inventor Michael J. Cadigan, Jr.
Michael J. Cadigan, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10908902Abstract: Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return.Type: GrantFiled: May 26, 2016Date of Patent: February 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Brian R. Prasky
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Patent number: 10754781Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.Type: GrantFiled: February 27, 2017Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
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Patent number: 10481912Abstract: Embodiments include method, systems and computer program products for variable branch target buffer line size for compression. In some embodiments, a branch target buffer (BTB) congruence class for a line of a first parent array of a BTB may be determined. A threshold indicative of a maximum number branches to be stored in the line may be set. A branch may be received to store in the line of the first parent array. A determination may be made that storing the branch in the line would exceed the threshold and the line can be responsively split into an even half line and an odd half line.Type: GrantFiled: June 24, 2016Date of Patent: November 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Brian R. Prasky
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Patent number: 10430195Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction including a first instruction address. The computer-implemented method further includes searching, by the processor, a stream-based index accelerator predictor one time for the stream; determining, by the processor, a prediction for a branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; and updating, by the processor, a stream-based index accelerator predictor with information indicative of the prediction.Type: GrantFiled: June 27, 2016Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Christian Jacobi, Daniel Lipetz, Anthony Saporito
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Patent number: 10423420Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.Type: GrantFiled: March 1, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
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Patent number: 10423419Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the updated prediction.Type: GrantFiled: June 27, 2016Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
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Patent number: 10394559Abstract: A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.Type: GrantFiled: December 13, 2016Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
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Patent number: 10379748Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.Type: GrantFiled: December 19, 2016Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney, Craig R. Walters
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Patent number: 10175893Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.Type: GrantFiled: July 26, 2017Date of Patent: January 8, 2019Assignee: International Business Machines CorporationInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney, Craig R. Walters
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Publication number: 20180246811Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.Type: ApplicationFiled: February 27, 2017Publication date: August 30, 2018Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
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Publication number: 20180173428Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney, Craig R. Walters
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Publication number: 20180173429Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.Type: ApplicationFiled: July 26, 2017Publication date: June 21, 2018Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney, Craig R. Walters
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Publication number: 20180165094Abstract: A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
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Patent number: 9934040Abstract: According to an aspect, virtualized weight perceptron branch prediction is provided in a processing system. A selection is performed between two or more history values at different positions of a history vector based on a virtualization map value that maps a first selected history value to a first weight of a plurality of weights, where a number of history values in the history vector is greater than a number of the weights. The first selected history value is applied to the first weight in a perceptron branch predictor to determine a first modified virtualized weight. The first modified virtualized weight is summed with a plurality of modified virtualized weights to produce a prediction direction. The prediction direction is output as a branch predictor result to control instruction fetching in a processor of the processing system.Type: GrantFiled: June 28, 2016Date of Patent: April 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Matthias D. Heizmann, Daniel Lipetz, Brian R. Prasky
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Publication number: 20170371668Abstract: Embodiments include method, systems and computer program products for variable branch target buffer line size for compression. In some embodiments, a branch target buffer (BTB) congruence class for a line of a first parent array of a BTB may be determined. A threshold indicative of a maximum number branches to be stored in the line may be set. A branch may be received to store in the line of the first parent array. A determination may be made that storing the branch in the line would exceed the threshold and the line can be responsively split into an even half line and an odd half line.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: James J. Bonanno, Michael J. Cadigan, JR., Brian R. Prasky
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Publication number: 20170371670Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz
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Publication number: 20170371672Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.Type: ApplicationFiled: March 1, 2017Publication date: December 28, 2017Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz
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Publication number: 20170371671Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction including a first instruction address. The computer-implemented method further includes searching, by the processor, a stream-based index accelerator predictor one time for the stream; determining, by the processor, a prediction for a branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; and updating, by the processor, a stream-based index accelerator predictor with information indicative of the prediction.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Christian Jacobi, Daniel Lipetz, Anthony Saporito
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Publication number: 20170344371Abstract: Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return.Type: ApplicationFiled: May 26, 2016Publication date: November 30, 2017Inventors: JAMES J. BONANNO, MICHAEL J. CADIGAN, JR., ADAM B. COLLURA, DANIEL LIPETZ, BRIAN R. PRASKY
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Publication number: 20170344373Abstract: Examples of techniques for distance-based branch prediction are disclosed.Type: ApplicationFiled: February 23, 2017Publication date: November 30, 2017Inventors: JAMES J. BONANNO, MICHAEL J. CADIGAN, Jr., ADAM B. COLLURA, DANIEL LIPETZ, BRIAN R. PRASKY