Abstract: Embodiments relate to optimizing an indirect call function. A compiler is provided to identify potential target functions and indicate the potential target functions in the program code. Additionally, the compiler determines and indicates in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module. A linker can read the indication the compiler made in the program code and optimize the indirect call function.

Abstract: Embodiments relate to using a local entry point with an indirect call function. A compiler is provided to determine and indicate in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. The compiler loads an address of a function through use of a symbolic reference. When the compiler determines that the value employed by the symbolic reference is used exclusively to perform an indirect function call, the compiler proceeds to resolve a local entry point address of the function, thereby reducing a quantity of operations to be executed.

Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler determines and indicates, in the program code, that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module, e.g. local-use-only. A linker or loader can read the indication the compiler made in the program code. The linker or loader use the local entry point associated with the target function if the target function is defined in the same module as the reference and is local-use-only.

Abstract: A method, system, and computer product for detecting a virtual object include transmitting a probe signal to objects, receiving an echo signal reflected by at least one object of the objects, generating scan data based on the echo signal, capturing one or more images of the objects, generating image data corresponding to the captured images, computing the scan data to identify each of the objects, computing the image data to identify each of the objects, and determining another object of the objects as a virtual object, responsive to determining that the another object is identified by the computation on the image data and is not identified by the computation on the scan data.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch cancelling instruction is being executed. In response to recognizing that the prefetch cancelling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch cancelling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause cancelling of the qualified prefetches that fit the criterion. In response to successful cancelling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.

Abstract: Processing prefetch memory operations and transactions. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, determining whether a priority of the remote processor is greater than a priority of a local processor. The write prefetch request is executed in response to a to a determination that the priority of the remote processor is greater than the priority of the local processor. Prefetch data produced by execution of the prefetch request is provided to the remote processor.

Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.

Abstract: Providing control over processing of a prefetch request in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. A processor generates a prefetch request and a tag that dictates processing the prefect request. A processor sends the prefetch request and the tag to a second processor. A processor generates a conflict indication based on whether a concurrent processing of the prefetch request and an atomic transaction by the second processor would generate a conflict with a memory access that is associated with the atomic transaction. Based on an analysis of the conflict indication and the tag, a processor processes (i) either the prefetch request or the atomic transaction, or (ii) both the prefetch request and the atomic transaction.

Abstract: A transaction is detected. The transaction has a begin-transaction indication and an end-transaction indication. If it is determined that the begin-transaction indication is not a no-speculation indication, then the transaction is processed.

Abstract: Embodiments relate to optimizing an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler is provided to identify potential target functions and indicate the potential target functions in the program code. Additionally, the compiler determines and indicates in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module. A linker can read the indication the compiler made in the program code and optimize the indirect call function.

Abstract: Techniques for processing instructions include receiving a plurality of instructions from a program counter (PC) operable to be fused into a PC-relative plus offset instruction. The technique also includes fusing the plurality of instructions into an internal operation (IOP) that specifies PC-relative addressing with an offset. The technique also includes computing a shared PC portion that includes one or more common upper bits of a PC address of each of the plurality of instructions. If the shared PC portion is different than a previously computed shared PC portion, the technique transmits the shared PC portion to one or more downstream components in the processor pipeline. The technique further includes transmitting the IOP with a representation of lower order bits of the PC address and processing the IOP.

Abstract: Embodiments relate to optimizing an indirect call function. More specifically, an indirect call function configuration comprises a first application module having a target function of the indirect function call, a second application module with a symbolic reference to the target function of the indirect function call, and a third application module to originate an indirect function call. A compiler identifies potential target functions and indicates the potential target functions in the program code. Additionally, the compiler determines and indicates in the program code that the function pointer value resulting from a non-call reference of a function symbol is solely used to perform indirect calls in the same module. A linker can read the indication the compiler made in the program code and optimize the indirect call function.

Abstract: Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a determination that execution of the prefetch request is predicted to cause an address conflict during an execution of a transaction of the local processor by determining an evaluation of the prefetch request prior to execution of the program instructions included in the prefetch request. The evaluation is based, at least in part, on (i) a comparison of a priority of the prefetch request with a priority of the transaction and (ii) a condition that exists in one or both of the local processor and the remote processor. Based on the evaluation, the local computer modifies program instructions that govern execution of the program instructions included in the prefetch request.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: Computer readable medium and apparatus for translating a sequence of instructions is disclosed herein. In one embodiment, an operation includes recognizing a candidate multi-instruction sequence, determining that the multi-instruction sequence corresponds to a single instruction, and executing the multi-instruction sequence by executing the single instruction.

Abstract: The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, and assigning a binary value to each first memory block section. An image of the load instruction is obtained and a pointer address is calculated from the image. It is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.