Patents by Inventor Michael Kugel
Michael Kugel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10529388Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: August 29, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20180374517Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: August 29, 2018Publication date: December 27, 2018Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 10096346Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: July 19, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20170316812Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9767872Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: July 28, 2016Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9761286Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: GrantFiled: August 24, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20170084314Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Patent number: 9589604Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: GrantFiled: September 17, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Patent number: 9564188Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: August 31, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9552851Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.Type: GrantFiled: August 31, 2015Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20160365130Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20160336049Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9384823Abstract: An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.Type: GrantFiled: September 19, 2014Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Kugel, Silke Penth, Raphael Polig, Tobias Werner
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Publication number: 20160086659Abstract: An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Inventors: Michael Kugel, Silke Penth, Raphael Polig, Tobias Werner
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Publication number: 20160071555Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: August 31, 2015Publication date: March 10, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Publication number: 20160072461Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.Type: ApplicationFiled: August 31, 2015Publication date: March 10, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 8942052Abstract: A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET.Type: GrantFiled: November 21, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: William V. Huott, Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel
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Patent number: 8918749Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.Type: GrantFiled: November 6, 2013Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Michael Kugel, Stefan Payer, Raphael Polig, Tobias Werner
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Patent number: 8837235Abstract: A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.Type: GrantFiled: March 6, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Yuen Hung Chan, Michael Kugel, Silke Penth, Tobias Werner
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Publication number: 20140140157Abstract: A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: William V. Huott, Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel