Abstract: A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data.

Abstract: An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.

Abstract: An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.

Abstract: An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).

Abstract: A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: A closure assembly and a method of installing the closure assembly are provided. A insertion opening is formed in water resistant barrier covering a rough opening that generally corresponds to a perimeter of the rough opening. A drainage system including a channel assembly is installed on a sill surface of the rough opening. The closure assembly is inserted into the rough opening and temporarily secured to the structure. At least one shim carried on the closure assembly is adjusted to level the closure assembly in the rough opening. A sealing member attached to the closure assembly is engaged with the water resistant barrier. A foam material is delivered into at least a portion of a space between perimeter edge surfaces of the closure assembly and inner surfaces of the rough opening to permanently secure the closure assembly within the rough opening.