Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Abstract: A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

Abstract: A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Abstract: The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the layer of polysilicon. The method further comprises forming a metal region in the recess and patterning the layer of polysilicon to define a gate stack comprised of the metal region and the layer of polysilicon.

Abstract: An improved series-connected transistor architecture and a method for forming the same are provided. Gate conductors for series connected transistors are patterned such that gate conductors on either side of a merged source/drain region which will not be contacted in the completed circuit are spaced more closely together than other gate conductors. In an embodiment of the method, these closely-spaced gate conductors have a spacing between facing sidewalls of less than about twice the expected sidewall spacer width for the process. After a first dopant impurity introduction, a conformal dielectric layer is deposited and portions of the dielectric layer are removed to form sidewall spacers. In the region between the closely-spaced gate conductors, the spacers are merged to form a continuous dielectric. This dielectric protects the substrate between the closely-spaced gate conductors from subsequent impurity introduction and salicide processes.

Abstract: An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region.

Abstract: In a plurality of series-coupled IGFET devices, wherein each pair of devices in the series shares a common source/drain terminal, only the source/drain regions acting as drain terminals are provided with a lightly-doped region. The presence of the lightly-doped source/drain regions in the portions of the source/drain regions acting as drain terminals provides protection against “hot-carrier” effects. By not having lightly-doped portions in portions of the source/drain regions acting as sources, the resistance resulting from the presence of the additional lightly-doped portions of the remaining source/drain regions in the series of IGFET devices results in lower resistance experienced by the conduction current. According to a second embodiment of the invention, only the non-shared source/drain terminal acting as drain terminal is provided with a lightly-doped region.

Abstract: A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.

Abstract: A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop.

Abstract: An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the substrate. The isolation structures are formed by providing a first mask to form trenches in the substrate. A layer of silicon dioxide is then deposited, filling the trenches and extending above the surface of the substrate. A second mask layer is formed. The second mask layer shadows the trench regions that were formed in the substrate. The silicon dioxide not shadowed by the second mask layer is removed, leaving isolation structures that extend both into the substrate and which rise above the substrate. A gate structure is formed in the region between two isolation structures, and, in the preferred embodiment, the gate structure extends above the substrate to the same height as the isolation structures. The isolation structures and the gate structure can be used to provide self-aligned doped source/drain regions.

Abstract: A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate.

Abstract: An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis which the gate conductor extends. The removed portions presents a partially retained region of lesser thickness than the fully retained region immediately adjacent thereto. An implant is then forwarded to the substrate adjacent and partially below the gate conductor. Only the partially retained portions allow a subset of the originally forwarded ions to pass into the substrate to form a lightly doped drain (LDD) between the channel and the drain. The partially retained region occurs only near the drain and not adjacent the source so that the LDD area is self-aligned between the edge of the conductor and a line of demarcation separating the fully retained portion and the partially retained portion.

Abstract: A wafer includes levels elevated above the wafer substrate or base substrate which includes separated substrates suitable for circuit device element formation. In one embodiment, a first level dielectric is formed over circuit devices having elements formed in the wafer substrate. Contacts from the circuit elements may extend to the surface of the first level dielectric. A second dielectric is formed on the first level dielectric and etched to create separated openings with some openings exposing contacts. The openings are filled with substrate material, thus forming elevated substrates and local interconnects where exposed contact top surfaces are present. The substrate material is suitable for circuit device fabrication. Additional levels of elevated substrates and concurrently formed local interconnects may be subsequently fabricated.

Abstract: A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate.