Abstract: A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop.

Abstract: A method for enhancing the thickness of a field oxide layer at perimeters of the field regions is presented. The use of a relatively thin pad oxide layer under a nitride layer reduces lateral encroachment of the field oxide layer into device active areas, but also results in undesirable elevational disparities in an upper surface of the field oxide layer near perimeters. Elevational disparities are created when the field oxide layer grows up and around vertical edges of remaining portions of the patterned nitride layer. An oxide deposition step followed by a directional etch process are used to fill in the elevational disparities, increasing the thickness of the field oxide layer at perimeters of the field regions. In a first embodiment, an oxide layer is deposited over the exposed surface following removal of remaining portions of the nitride layer over device active areas.

Abstract: A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator and a gate electrode, the gate electrode having opposing first and second sidewalls defining the length of the gate electrode and a top surface. Lightly doped source and drain regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source and drain regions are implanted into the semiconductor substrate.

Abstract: A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-doped N+ source/drain regions and the channel, beneath the oxide sidewall spacer.

Abstract: A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

Abstract: A method of making MOS integrated circuits employs high-pressure oxidation of the surface of a silicon slice to create thermal field oxide for device isolation. The implant used prior to this oxidation to provide the channel-stop regions beneath the field oxide may be at a lower dosage, and yet the field-transistor threshold voltage is maintained at a high level. Thus, encroachment of the channel stop impurity into the transistor channel is minimized, and higher density devices are permitted.

Abstract: A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-doped N+ source/drain regions and the channel, beneath the oxide sidewall spacer.