Abstract: A semiconductor device is analyzed and manufactured using a heat-exchange probe. According to an example embodiment of the present invention, a heat-exchange probe is controlled to exchange heat to a portion of a semiconductor device using sub-micron resolution. In one implementation, sub-micron resolution is achieved using a navigational arrangement, such as microscope, adapted to direct light to within about one micron of a target circuit portion on a plane of the device. In another implementation, a physical heat probe tip (e.g., a metal probe having about a one micron diameter probe tip) is navigated to a selected portion of the device using sub-micron navigational resolution. In each of these implementations, as well as others, the heat exchange is preponderantly confined to within about a one micron radius of a target portion of circuitry on lateral plane of the device.

Abstract: Various apparatus and methods for enhancing hot-electron luminescence in an integrated circuit are provided. In one aspect, an apparatus is provided that includes a first circuit device coupled to a first voltage source that is operable to bias the first circuit device to a first voltage, and a second circuit device that has a first input coupled to the first voltage source and a junction defining a first side and a second side. One of the first and second sides is coupled to a second voltage source that is independent of the first voltage source and capable of selectively biasing the one of the first and second sides at a second voltage higher than the first voltage. The second device is operable to emit a hot-electron induced photon upon entry into saturation.

Abstract: An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that improves the ability to obtain a signal from the SOI structure. According to one example embodiment, a stimulating device is adapted to stimulate an integrated circuit having SOI structure. An electro-optic probe arrangement is focused on a selected portion of the integrated circuit in a manner that makes possible the detection of a response to the stimulation from the SOI selected portion. In this manner electro-optic probing portions of an integrated circuit having SOI structure is enhanced.

Abstract: Various methods of hot-electron imaging a workpiece are provided. In one aspect, a method of examining a workpiece is provided that includes directing a first photon at a photodetector at a first known time and stimulating a circuit device of the workpiece at a second known time to produce a condition in the circuit device conducive to photon emission. At least one photon emitted by the circuit device in response to the stimulation is detected. The first photon increases the quantum efficiency of the photodetector in detecting the at least one photon. The detection of the at least one photon relative to the first known time and the second known time is time correlated to temporally distinguish the first photon and the at least one photon and to temporally correlate the stimulation of the circuit device to the detection of the at least one photon.

Abstract: According to an example embodiment of the present invention, a portion of substrate in the back side of a semiconductor chip is removed as a function of photons emitted through substrate remaining at the back side. The use of emitted photons is used to control the substrate removal process.

Abstract: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.

Abstract: An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that enhances the ability to detect photoemissions from the die. According to an example embodiment of the present invention, one of two or more lenses having a higher relative photon count is identified and used to analyze a semiconductor die. The die has at least a portion of the insulator of the SOI structure exposed, and photon emissions are detected using each lens via the exposed insulator in response to the die being stimulated. The number of photons detected using each lens is compared, and the lens having a higher photon count rate is identified, optimizing the photon count for the particular type of die preparation used to expose the insulator. The identified lens is then used with the high-speed detector to detect photoemissions from the die, and the detected photoemissions are used to analyze the die.

Abstract: Methods and apparatus for inspecting a sample are provided. In one aspect, a method of inspection is provided that includes generating an entangled set of particle beams and directing one of the entangled set of particle beams to a location of a workpiece. One of the entangled set of particle beams interacts with the location of the workpiece. One of the entangled set of particle beams is observed after the interaction with the location of the workpiece to inspect the location of the workpiece.

Abstract: According to one aspect of the disclosure, laser-thermal annealing is used to clear an imaging path through the back side of a semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For many applications, thinning results in the formation of crystal defects that inhibit the ability to obtain images through the back side of the semiconductor device. One example embodiment overcomes this problem by thinning via laser-chemical etching the back side of the semiconductor device under a pressure exceeding a threshold level, and then reducing the pressure to a level below the threshold level and scanning the back side of the semiconductor device using a laser at a reduced power level. IR microscopy is then used to capture an image of a circuit in the circuit side of the semiconductor device through the back side of the semiconductor device. One particular example application is directed to a flip-chip semiconductor device.

Abstract: According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

Abstract: An apparatus, system, and method are provided for testing an integrated circuit with a probe card having optical fibers. The optical fibers of the probe card are fixed in alignment with test structures in the integrated circuit, and each optical fiber is coupled to an avalanche photo-diode for measuring photoemissions from the test structures. The photoemissions can be analyzed to verify correct circuit behavior. The optical fibers can be alternatives or complements to electrically conductive probes of the probe card.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the hack side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement from the die that is used for analysis.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by operating a die and detecting a response that is used to analyze selected characteristics of the die. According to an example embodiment of the present invention, a die having a thinned backside is provided for analysis. The die is operated so that one or more portions of circuitry in the die are near a state-changing transition between a failed mode and a recovered mode. An electron-beam probe is directed to the thinned backside, and the probe electrically couples a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry and, thereby, causes the circuitry to undergo a state-changing transition. A response from the circuitry related to the transition is detected and used to analyze the die. In this manner, portions of the die being affected by altered timing margins can be detected.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.

Abstract: A method and system providing single point high spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A photo-diode optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

Abstract: Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled.

Abstract: The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Abstract: An apparatus and method are presented for identifying and mapping functional failures in an integrated circuit (IC) due to timing errors therein based on the generation of functional failures in the IC. This is done by providing a set of input test vectors to the IC and adjusting one or more: of the IC voltage, temperature or clock frequency; the rate at which the test vectors are provided to the IC; or the power level of a focused laser beam used to probe the IC and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures. The present invention has applications for optimizing the design and fabrication of ICs, for failure analysis, and for qualification or validation testing of ICs.

Abstract: A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT).

Abstract: Useful in connection with IC testing at a post-manufacture stage, an example embodiment is directed to use of photoluminescence PL spectroscopy for detecting contaminants in circuit materials. According to one example embodiment, a system includes a test fixture arranged to secure a die and includes a laser-scanning microscope. This system is arranged to direct a laser beam at a target material in the die and receives a secondary PL component remitted from the target circuit material. A contaminant in the target material is indicated by the reception of the secondary PL component.