Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)xHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.