Patents by Inventor Michael Raymond Weatherspoon

Michael Raymond Weatherspoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10056670
    Abstract: A method has been described for making an electrical structure having an air dielectric and includes forming a first subunit including a sacrificial substrate, an electrically conductive layer including a first metal on the sacrificial substrate, and a sacrificial dielectric layer on the sacrificial substrate and the electrically conductive layer. The method further includes forming a second subunit including a dielectric layer and an electrically conductive layer thereon including the first metal, and coating a second metal onto the first metal of one or more of the first and second subunits. The method also includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate and sacrificial dielectric layer to thereby form the electrical structure having the air dielectric.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 21, 2018
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Robert Patrick Maloney, David M. Smith
  • Patent number: 9892984
    Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 13, 2018
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr.
  • Patent number: 9691698
    Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 27, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, David B. Nicol, Louis Joseph Rendek, Jr.
  • Patent number: 9681543
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 13, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Travis L. Kerby, Casey Philip Rodriguez, Michael Raymond Weatherspoon
  • Patent number: 9655236
    Abstract: A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 16, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Casey Philip Rodriguez
  • Publication number: 20160351459
    Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.
    Type: Application
    Filed: August 11, 2016
    Publication date: December 1, 2016
    Inventors: MICHAEL RAYMOND WEATHERSPOON, LOUIS JOSEPH RENDEK, JR.
  • Publication number: 20160322284
    Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: MICHAEL RAYMOND WEATHERSPOON, DAVID B. NICOL, LOUIS JOSEPH RENDEK, JR.
  • Patent number: 9443789
    Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 13, 2016
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr.
  • Patent number: 9420687
    Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: August 16, 2016
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, David B. Nicol, Louis Joseph Rendek, Jr.
  • Publication number: 20160174371
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: LOUIS JOSEPH RENDEK, JR., TRAVIS L. KERBY, CASEY PHILIP RODRIGUEZ, MICHAEL RAYMOND WEATHERSPOON
  • Patent number: 9293438
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 22, 2016
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Casey Philip Rodriguez, Travis L. Kerby, Michael Raymond Weatherspoon
  • Publication number: 20160006100
    Abstract: A method has been described for making an electrical structure having an air dielectric and includes forming a first subunit including a sacrificial substrate, an electrically conductive layer including a first metal on the sacrificial substrate, and a sacrificial dielectric layer on the sacrificial substrate and the electrically conductive layer. The method further includes forming a second subunit including a dielectric layer and an electrically conductive layer thereon including the first metal, and coating a second metal onto the first metal of one or more of the first and second subunits. The method also includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate and sacrificial dielectric layer to thereby form the electrical structure having the air dielectric.
    Type: Application
    Filed: September 18, 2015
    Publication date: January 7, 2016
    Inventors: MICHAEL RAYMOND WEATHERSPOON, LOUIS JOSEPH RENDEK, JR., LAWRENCE WAYNE SHACKLETTE, ROBERT PATRICK MALONEY, DAVID M. SMITH
  • Patent number: 9159485
    Abstract: A method is for making an electrical inductor. The method includes forming a first subunit having a sacrificial substrate, and an electrically conductive layer defining the electrical inductor and including a first metal on the sacrificial substrate. The method includes forming a second subunit having a dielectric layer and an electrically conductive layer thereon defining electrical inductor terminals and having the first metal, and coating a second metal onto the first metal of one of the first and second subunits. The method includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: October 13, 2015
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Robert Patrick Maloney, David M. Smith
  • Patent number: 9142497
    Abstract: A method has been described for making an electrical structure having an air dielectric and includes forming a first subunit including a sacrificial substrate, an electrically conductive layer including a first metal on the sacrificial substrate, and a sacrificial dielectric layer on the sacrificial substrate and the electrically conductive layer. The method further includes forming a second subunit including a dielectric layer and an electrically conductive layer thereon including the first metal, and coating a second metal onto the first metal of one or more of the first and second subunits. The method also includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate and sacrificial dielectric layer to thereby form the electrical structure having the air dielectric.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: September 22, 2015
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Robert Patrick Maloney, David M. Smith
  • Patent number: 9059317
    Abstract: A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 16, 2015
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Michael Raymond Weatherspoon, Casey Philip Rodriguez, David Nicol
  • Publication number: 20150069621
    Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Harris Corporation
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, JR.
  • Publication number: 20150053468
    Abstract: A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: MICHAEL RAYMOND WEATHERSPOON, LOUIS JOSEPH RENDEK, JR., LAWRENCE WAYNE SHACKLETTE, CASEY PHILIP RODRIGUEZ
  • Publication number: 20150009644
    Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: Louis Joseph RENDEK, JR., Casey Philip Rodriguez, Travis L. Kerby, Michael Raymond Weatherspoon
  • Publication number: 20140376197
    Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventors: MICHAEL RAYMOND WEATHERSPOON, DAVID B. NICOL, LOUIS JOSEPH RENDEK, JR.
  • Patent number: 8912641
    Abstract: An electronic package includes a printed wiring board (PWB) having a die-receiving cavity therein, a semiconductor die in the die-receiving cavity and coupled to the PWB, and a lid mating ring at an upper surface of the PWB surrounding the die-receiving cavity. The lid mating ring has spaced apart pillar-receiving openings therein. A lid is coupled to the lid mating ring and covers the semiconductor die within the die-receiving cavity. The lid includes a liquid crystal polymer (LCP) layer, and spaced apart pillars extending downwardly from a lower surface of the LCP layer and received in corresponding ones of the spaced apart pillar-receiving openings.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 16, 2014
    Assignee: Harris Corporation
    Inventors: Louis Joseph Rendek, Jr., Michael Raymond Weatherspoon