Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.

Abstract: Memory circuitry 2 includes an array 4 of bit cells 6. One or more boost capacitors C1, C2 are connected to bit lines 8 running through the array 4 and serve to store a sample charge with a sample voltage difference during a sampling configuration of the boost capacitors C1, C2. A boost configuration is subsequently adopted in which the boost capacitors C1, C2 are connected with a different plurality to respective bit lines 8 such that the sample voltage difference is added to the voltage change within the bit line produced by the bit line cell 6 so as to generate an increased magnitude change in voltage which is supplied to sense amplifier circuitry 12.

Abstract: A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.

Abstract: Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

Abstract: Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

Abstract: An electronic device has an energy storage device and circuitry supplied with a storage device voltage from the energy storage device. A supervisor circuit enables the circuitry in response to the storage device exceeding an enable threshold voltage. The supervisor circuit detects a resistance parameter which is indicative of an internal resistance of the energy storage device and adjusts the enable threshold voltage based on the resistance parameter.

Abstract: Implementations related to system and techniques for providing audio news reports are discussed. A computer-implemented method includes identifying, with a computer system, one or more news preferences for a first user, selecting a plurality of news stories, wherein particular ones of the new stories are determined to be responsive to the news preferences for the first user and comprise audio versions of stories converted automatically from textual news stories, assembling, with the computer system and for the first user, an audio news report that includes the audio versions of the selected news stories, and delivering, to a computing device, the assembled audio news report.

Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period.

Abstract: A level conversion circuit has a keeper circuit for retaining an intermediate output node at a high output level to avoid it floating due to leakage through a pullup transistor in a shifting circuit. Thin oxide and thick oxide versions of the level conversion circuit can be provided. The level conversion circuit enables higher performance, reduced power consumption and reduced susceptibility to process variation compared to previous level conversion designs.

Abstract: Signal value storage circuitry 2 is provided which includes a first transistor stack, a second transistor stack and a third transistor stack. The signal value storage circuitry is controlled by a single clock signal. Keeper transistors and isolation transistors serve to permit static operation of the signal value storage circuitry (i.e. the clock signal may be stopped without losing state) and to prevent contention within the circuitry.

Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.

Abstract: Memory circuitry 2 includes an array 4 of bit cells 6. One or more boost capacitors C1, C2 are connected to bit lines 8 running through the array 4 and serve to store a sample charge with a sample voltage difference during a sampling configuration of the boost capacitors C1, C2. A boost configuration is subsequently adopted in which the boost capacitors C1, C2 are connected with a different plurality to respective bit lines 8 such that the sample voltage difference is added to the voltage change within the bit line produced by the bit line cell 6 so as to generate an increased magnitude change in voltage which is supplied to sense amplifier circuitry 12.

Abstract: Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.

Abstract: Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.

Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.

Abstract: A business object model, which reflects data that is used during a given business transaction, is utilized to generate interfaces. This business object model facilitates commercial transactions by providing consistent interfaces that are suitable for use across industries, across businesses, and across different departments within a business during a business transaction.

Abstract: Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.

Abstract: A sensor assembly for measuring relative rotary movement about a pivot joint having an axis of rotation between a first member and a second member.

Abstract: A work vehicle includes a frame and an axle assembly coupled to the frame, including a first axle shaft and coil substantially disposed in an axle housing. A first wheel couples to the first axle shaft of the axle assembly. An axle lubricating fluid is disposed within the axle housing. A cooling circuit fluidly coupled to the axle assembly circulates cooling fluid therethrough. The coil conducts cooling fluid through the first axle housing separately from the lubricating fluid. A cooling fluid circuit is selectively fluidly coupled to the first coil to circulate the cooling fluid therethrough.

Abstract: An apparatus including a first circuit and a second circuit connected in parallel to the bidirectional communication path, and one of the first and second circuits being an active circuit monitoring a value of the data signal on the bidirectional communication path while the other of the first and second circuits being a passive circuit that is not monitoring the value of the data signal. The active circuit initially starts in a low gain state, but on detection of a transition by transition detection circuitry, it enters a high gain state where the switch circuitry disconnects the transition detection circuitry from the bidirectional communication path, and the drive circuitry is activated in order to drive the data signal on the bidirectional communication path to the opposite value. Once the data signal has been driven to the opposite value, the active circuit and the passive circuits switch states.