Patents by Inventor Michael Van BusKirk
Michael Van BusKirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170018555Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Patent number: 9524971Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: February 5, 2015Date of Patent: December 20, 2016Inventors: Srinivasa R. Banna, Michael A. van Buskirk, Timothy Thurgate
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Patent number: 9431101Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.Type: GrantFiled: January 19, 2015Date of Patent: August 30, 2016Assignee: Adesto Technologies CorporationInventors: Foroozan Sarah Koushan, Michael A. Van Buskirk
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Patent number: 9368206Abstract: In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.Type: GrantFiled: July 7, 2014Date of Patent: June 14, 2016Assignee: Adesto Technologies CorporationInventors: John Dinh, Ming Sang Kwan, Venkatesh P. Gopinath, Derric Lewis, Shane Hollmer, John R. Jameson, Michael Van Buskirk
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Patent number: 9330755Abstract: A circuit can include at least one two terminal element programmable between at least two impedance states; a write section configured to place the element into different impedance states in a write mode; and a read section configured to generate an output value corresponding to the impedance state of at least one element in a read mode; wherein the at least one element draws substantially no current in a standard mode that is different from the write and read modes.Type: GrantFiled: February 9, 2014Date of Patent: May 3, 2016Assignee: Adesto Technologies CorporationInventor: Michael A. Van Buskirk
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Patent number: 9099176Abstract: A resistive switching memory device can include a plurality of resistive memory cells, where each of the resistive memory cells includes: (i) a first diode having an anode coupled to a first word line and a cathode coupled to a common node; (ii) a second diode having an anode coupled to the common node and a cathode coupled to a second word line; and (iii) a resistive storage element having an anode coupled to a bit line and a cathode coupled to the common node, wherein the resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction.Type: GrantFiled: April 18, 2014Date of Patent: August 4, 2015Assignee: Adesto Technologies CorporationInventor: Michael Van Buskirk
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Patent number: 9093311Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: June 9, 2014Date of Patent: July 28, 2015Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Publication number: 20150162079Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.Type: ApplicationFiled: January 19, 2015Publication date: June 11, 2015Inventors: Foroozan Sarah Koushan, Michael A. Van Buskirk
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Publication number: 20150155285Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Applicant: Micron Technology, Inc.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Patent number: 9019759Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: October 1, 2013Date of Patent: April 28, 2015Assignee: Micron Technology, Inc.Inventors: Srinivasa R. Banna, Michael A. Van Buskirk, Timothy Thurgate
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Publication number: 20150076442Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.Type: ApplicationFiled: November 24, 2014Publication date: March 19, 2015Inventor: Michael A. Van Buskirk
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Patent number: 8982633Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: GrantFiled: July 30, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Srinivasa R. Banna, Michael A. Van Buskirk
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Patent number: 8976568Abstract: A memory device can include a plurality of memory cells each comprising at least one programmable impedance memory element; a programming circuit coupled to the memory elements and configured to apply at least one time varying pulse to memory elements to place them into one of at least two different impedance states; and a programming voltage source coupled to the programming circuit configured to generate the at least one time varying pulse; wherein the time varying pulse decreases and increases in potential while having an overall increase in one voltage polarity.Type: GrantFiled: January 18, 2013Date of Patent: March 10, 2015Assignee: Adesto Technologies CorporationInventors: John Ross Jameson, III, Michael A. Van Buskirk
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Patent number: 8952351Abstract: A memory device can include a plurality of memory elements formed over a substrate, including a plurality of first electrodes, each having a top surface and opposing side surfaces, a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and a memory material formed between each first electrode and an adjacent second electrode, the memory material being in contact with the opposing side surfaces of each first electrode and not in contact with the top surface of the first electrodes; wherein the memory material is electrically programmable between at least two different resistance states, and the lateral direction is parallel to a top surface of the substrate.Type: GrantFiled: July 30, 2014Date of Patent: February 10, 2015Assignee: Adesto Technologies CorporationInventor: Michael A. Van Buskirk
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Patent number: 8953362Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.Type: GrantFiled: September 11, 2012Date of Patent: February 10, 2015Assignee: Adesto Technologies CorporationInventors: Foroozan Sarah Koushan, Michael A. Van Buskirk
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Patent number: 8947965Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.Type: GrantFiled: November 19, 2012Date of Patent: February 3, 2015Assignee: Micron Technology Inc.Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
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Patent number: 8912517Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.Type: GrantFiled: September 24, 2012Date of Patent: December 16, 2014Assignee: Adesto Technologies CorporationInventor: Michael A. Van Buskirk
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Publication number: 20140293676Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.Type: ApplicationFiled: March 3, 2014Publication date: October 2, 2014Inventors: Wei Ti Lee, Janet Wang, Chakravarthy Gopalan, Jeffrey Allan Shields, Yi Ma, Kuei Chang Tsai, John Sanchez, John Ross Jameson, Michael Van Buskirk, Venkatesh P. Gopinath
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Publication number: 20140291763Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: ApplicationFiled: June 9, 2014Publication date: October 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. VAN BUSKIRK, Christian CAILLAT, Viktor I. KOLDIAEV, Jungtae KWON, Pierre C. FAZAN
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Patent number: 8748959Abstract: A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: March 31, 2010Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I Koldiaev, Jungtae Kwon, Pierre C. Fazan