Patents by Inventor Michael Van BusKirk
Michael Van BusKirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140029360Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: October 1, 2013Publication date: January 30, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Patent number: 8624219Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.Type: GrantFiled: April 12, 2012Date of Patent: January 7, 2014Assignee: Adesto Technologies CorporationInventors: John Ross Jameson, Antonio R. Gallo, Foroozan Sarah Koushan, Michael A. Van Buskirk
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Publication number: 20140003125Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.Type: ApplicationFiled: September 11, 2012Publication date: January 2, 2014Applicant: ADESTO TECHNOLOGIES CORPORATIONInventors: Foroozan Sarah Koushan, Michael A. Van Buskirk
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Publication number: 20140003144Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: ApplicationFiled: August 30, 2013Publication date: January 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Publication number: 20130315000Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK
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Patent number: 8547738Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: March 14, 2011Date of Patent: October 1, 2013Assignee: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 8531878Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: GrantFiled: May 17, 2011Date of Patent: September 10, 2013Assignee: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 8498157Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: GrantFiled: May 24, 2010Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk
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Patent number: 8400811Abstract: Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.Type: GrantFiled: April 27, 2010Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventors: Eric S. Carman, Michael A. Van Buskirk, Yogesh Luthra
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Publication number: 20120307568Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.Type: ApplicationFiled: June 6, 2011Publication date: December 6, 2012Applicant: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Publication number: 20120294083Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: ApplicationFiled: May 17, 2011Publication date: November 22, 2012Applicant: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 8315099Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.Type: GrantFiled: July 27, 2010Date of Patent: November 20, 2012Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
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Publication number: 20110222356Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: March 14, 2011Publication date: September 15, 2011Applicant: Innovative Silicon ISi SAInventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 7902086Abstract: Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable molecule that can be preferentially oxidized over the carrier ions/electrodes.Type: GrantFiled: December 8, 2006Date of Patent: March 8, 2011Assignee: Spansion LLCInventors: Swaroop Kaza, David Gaun, Michael A. Van Buskirk
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Publication number: 20110019482Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.Type: ApplicationFiled: July 27, 2010Publication date: January 27, 2011Applicant: Innovative Silicon ISi SAInventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
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Publication number: 20100322006Abstract: A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Inventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael Van Buskirk
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Publication number: 20100296327Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.Type: ApplicationFiled: May 24, 2010Publication date: November 25, 2010Applicant: Innovative Silicon ISi SAInventors: Srinivasa Rao Banna, Michael A. Van Buskirk
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Publication number: 20100271858Abstract: Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.Type: ApplicationFiled: April 27, 2010Publication date: October 28, 2010Applicant: Innovative Silicon ISi SAInventors: Eric Scott Carman, Michael A. Van Buskirk, Yogesh Luthra
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Publication number: 20100259964Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: ApplicationFiled: March 31, 2010Publication date: October 14, 2010Applicant: Innovative Silicon ISi SAInventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Patent number: 7672161Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.Type: GrantFiled: April 30, 2007Date of Patent: March 2, 2010Assignee: Spansion LLCInventors: Ping Hou, Eugen Gershon, Michael A. Van Buskirk