Abstract: An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable (“flex cable”) secured to the PCB. The apparatus also includes a daughtercard having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector which provides an electrically conductive connection between the first flex cable and the second flex cable. The connector is positioned to sandwich a portion of the first flex cable between the connector and the PCB.

Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.

Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.

Abstract: In some embodiments, the invention includes a system having first, second, third and fourth modules; and a circuit board including first, second, third, and fourth module connectors to receive the first and second modules, respectively. The system includes among other things a first group of paths of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, back to the second module connector, to terminations, wherein the first group of paths include a first short loop through section in the first module and a second short loop through section in the second module, to each couple to stubs for corresponding first and second chips of the first and second modules.

Abstract: A system and method for increasing data transfer rate is disclosed. A digital signal waveform that contains one bit of information for every bit time of the digital signal waveform is received. Every three bits of the digital signal waveform is buffered and encoded. The encoding produces an encoded waveform that contains three bits of information for each bit time of the digital signal waveform, therefore, increasing the data transfer rate of the digital signal waveform.

Abstract: A method is provided for designing a computer assembly. This may include obtaining a design of the computer assembly having a transmission line and a connection portion, and matching an impedance value of the transmission line to an impedance value of the connection portion so as to obtain a desired filter characteristic. A computer assembly may also be provided that includes a motherboard, a module and a transmission line. A connection transition may be designed such that an impedance of the transmission line matches an impedance of the connection transition and to obtain a desired filter characteristic.

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: A computer motherboard is described. That motherboard includes a memory controller and a memory section. A first trace couples the memory controller to the memory section, and a second trace couples the memory controller to the memory section. The first trace is joined with the second trace at the memory controller, the second trace is routed in parallel with the first trace, and the second trace is longer than the first trace. Also described is a computer system that includes this motherboard and a memory card.

Abstract: A computer assembly is described. The computer assembly includes a motherboard and a socket mounted to the motherboard. The socket, which enables the motherboard to receive a memory card, has a mounting pin that is inserted into a via that is formed in the motherboard. A stub trace is coupled to the via to add capacitance at the via.

Abstract: A memory module is described. That memory module includes a memory device and a signal trace that has an unloaded portion and a loaded portion. The loaded portion has a first section and a second section. The memory device includes an input connection and an output connection. The first section of the loaded portion of the signal trace is coupled to the input connection and the second section of the loaded portion of the signal trace is coupled to the output connection. The impedance of the loaded portion is higher than it would have been if the first and second sections had been coupled to the same memory device connection.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first clock path of conductors to carry a first clock signal to first, second, third, and fourth chips on the first module and then to first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module.

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Abstract: A method and apparatus for the multi-level coding for communication for computer bus data transfers are described. An input signal and delayed versions of the input are combined to create an encoded output signal. An input signal and delayed versions of the output are combined to create a decoded output signal.

Abstract: A continuity module for a memory channel for a computer system. The continuity module includes a connecting member for coupling the continuity module to a socket that is coupled to a motherboard. The continuity module also includes a printed circuit board, which is coupled to the connecting member. The printed circuit board includes a signal trace that is coupled to a capacitive load. In preferred embodiments, the capacitive load comprises a plurality of vias and/or stub traces, which are coupled to the signal trace.

Abstract: A method and apparatus for a selectable RON driver impedance is described. The method includes the detection of a system memory configuration within a memory channel coupled to a chipset driver/receiver. Once the system memory configuration is detected, a driver output impedance of the chipset driver is set according to the detected system memory configuration. As a result, by dynamically setting the driver output impedance according to the detected system memory configuration, voltage swings, as well as reflections, along the memory bus transmission lines are avoided. Consequently, the amount of time required for a signal to propagate along a memory bus from the chipset driver to the actual memory device is effectively reduced and thereby increases a total interconnect timing budget.

Abstract: A printed circuit board is described. That printed circuit board includes a capacitive load that is coupled to a signal trace. The signal trace has a first section and a second section. The first section is positioned between the capacitive load and the second section. The second section has a first width, and the first section includes first and second lines that each have a width that is smaller than the first width.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first clock path of conductors to carry a first clock signal to first, second, third, and fourth chips on the first module and then to first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: In some embodiments, the invention includes a system having first, second, third and fourth modules; and a circuit board including first, second, third, and fourth module connectors to receive the first and second modules, respectively. The system includes among other things a first group of paths of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, back to the second module connector, to terminations, wherein the first group of paths include a first short loop through section in the first module and a second short loop through section in the second module, to each couple to stubs for corresponding first and second chips of the first and second modules.