Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Abstract: System and method for increasing data transfer rate. A digital signal waveform that contains one bit of information for every bit time of the digital signal waveform is received. Every three bits of the digital signal waveform is buffered and encoded. The encoding produces an encoded waveform that contains three bits of information for each bit time of the digital signal waveform, therefore, increasing the data transfer rate of the digital signal waveform.

Abstract: A printed circuit board is described. That printed circuit board includes a capacitive load that is coupled to a signal trace. The signal trace has a first section and a second section. The first section is positioned between the capacitive load and the second section. The second section has a first width, and the first section includes first and second lines that each have a width that is smaller than the first width.

Abstract: A memory module is described. That memory module includes a memory device and a signal trace that has an unloaded portion and a loaded portion. The loaded portion has a first section and a second section. The memory device includes an input connection and an output connection. The first section of the loaded portion of the signal trace is coupled to the input connection and the second section of the loaded portion of the signal trace is coupled to the output connection. The impedance of the loaded portion is higher than it would have been if the first and second sections had been coupled to the same memory device connection.

Abstract: A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The first signal trace has a relatively thin section and a relatively thick section. The multi-layer printed circuit board also includes a via that couples the first signal trace to the second signal trace. The first signal trace's relatively thin section is located between its relatively thick section and the via.

Abstract: A memory module includes a first memory bus. A memory repeater hub is coupled to the first memory bus. A second memory bus is coupled in series with the memory repeater hub.

Abstract: A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The multi-layer printed circuit board includes a via that couples a signal transmitting component to the second signal trace and a throttling member, which is coupled to the first signal trace. The throttling member reduces the speed at which a first signal routed over the first signal trace travels when compared to the speed at which that signal would have traveled had the throttling member been absent.

Abstract: A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad coupled to a first contact on the first component with a second landpad coupled to a corresponding first contact on the second component. A second signal line connects a third landpad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line.

Abstract: A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.

Abstract: An assembly featuring a substrate and a plurality of components. The plurality of components are packaged to be connected in a vertical orientation to the substrate. These components include (i) a vertical chip-scale package (CSP), (ii) an integrated circuit die and (iii) an interconnect. Including a plurality of connection leads, the vertical CSP contains the die which is generally situated along a vertical plane. The interconnect, capable of transferring information between the plurality of connection leads and the integrated circuit die, includes a first segment generally perpendicular to the vertical plane and connected to at least one connection lead. The interconnect further includes a second segment generally in parallel to the vertical plane and connected to the integrated circuit die.

Abstract: Attachment of electronics to optical devices is made by supporting the optical devices on a heat spreader card and the electronics on a separate circuit card. Each card has at least a first major surface, with an optical transducing subassembly mounted perpendicularly from the major surface of the heat spreader card. Electronics, except for transducing elements, are placed on the circuit card. The only direct attachment between the circuit card and the heat spreader card is one or more flexible cables attached to the respective major surfaces. This arrangement mechanically isolates the circuit card from the heat spreader card. The flexible cables include electrical conductors held positionally in a polyimide matrix, which provides for thermal isolation of the heat spreader card and the circuit card.