Abstract: Systems and methods are directed to efficient management of processor resources, particularly General Purpose Registers (GPRs), for example to minimize pipeline flushes prevent deadlocks by counting GPRs instead of allocating them to specific blocks of code. Blocks of code are allowed to execute if the Free GPRs count is adequate. The method contemplates counting the number of Register Writers in blocks of code which will write to GPRs which are in process of executing, and counting the GPRs which are available instead of merely allocating them to dedicated use by a block of code, or an instruction in a block of code. Because blocks do not run if there is not enough GPRs available for the block, deadlocks and pipeline flushes due to lack of resources can be minimized.

Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry.

Abstract: Caching instruction block header data in block architecture processor-based systems is disclosed. In one aspect, a computer processor device, based on a block architecture, provides an instruction block header cache dedicated to caching instruction block header data. Upon a subsequent fetch of an instruction block, cached instruction block header data may be retrieved from the instruction block header cache (if present) and used to optimize processing of the instruction block. In some aspects, the instruction block header data may include a microarchitectural block header (MBH) generated upon the first decoding of the instruction block by an MBH generation circuit. The MBH may contain static or dynamic information about the instructions within the instruction block. As non-limiting examples, the information may include data relating to register reads and writes, load and store operations, branch information, predicate information, special instructions, and/or serial execution preferences.

Abstract: A chute control assembly for a snow thrower having a housing, handle, and a chute includes a control mechanism, a connecting mechanism, and a guide mechanism. The control mechanism includes an actuator mechanism that allows an operator to manually control the orientation of the chute from a position spaced apart from the chute. The connecting mechanism transfers rotation of the actuator mechanism to the guide mechanism. The guide mechanism is attached to the chute and rotates and adjust the orientation of the chute in response to rotation of the actuator mechanism in order to change the direction that snow is thrown from the snow thrower.

Abstract: A method is provided for preparing a hair dye color mixture. The method includes: providing a control system having at least a memory, input controls, and a display; storing in the memory at least one formula, the formula including one or more colorants and/or dye blending materials, and wherein each colorant and/or blending material is separately assigned to an initial product brand; receiving input from the input controls to change a colorant and/or blending material from the initial product brand to one or more subsequent product brands, and wherein the control system recalculates components of the formula using the one or more subsequent product brands in response to receiving input from the input controls; and matching the color of the hair dye color mixture made from colorants and/or dye blending materials of the initial product brand using colorants and/or dye blending materials of the one or more subsequent product brands, in response to the input.

Abstract: Systems and methods for deduplication and disambiguation are disclosed. In example embodiments, a server accesses stored information about a first entity and stored information about a second entity. The server determines, based on the accessed stored information about the first entity and the accessed stored information about the second entity, a set of information items known about both the first entity and the second entity. The server computes, based on the set of information items, a probability that the first entity corresponds to the second entity by computing one or more expressiveness scores corresponding to a value of a first information item and a value of a second information item from the set of information items. The server provides, as a digital transmission, an output representing the computed probability.

Abstract: Systems and methods for selective refresh of a cache, such as a last-level cache implemented as an embedded DRAM (eDRAM). A refresh bit and a reuse bit are associated with each way of at least one set of the cache. A least recently used (LRU) stack tracks positions of the ways, with positions towards a most recently used position of a threshold comprising more recently used positions and positions towards a least recently used position of the threshold comprise less recently used positions. A line in a way is selectively refreshed if the position of the way is one of the more recently used positions and if the refresh bit associated with the way is set, or the position of the way is one of the less recently used positions and if the refresh bit and the reuse bit associated with the way are both set.

Abstract: A system for correcting network planning data includes a planning repository containing information related to network traffic, network element locations and network element connectivity. The system further includes a repository that includes a plurality of call data records. In addition, the system includes an information processing system including a processor and a memory device coupled to the processor. The memory device contains a set of instructions that, when executed by the processor, cause the processor to receive location data associated with a wireless network cell from a plurality of devices connected to the wireless network. The set of instructions further causes the processor to identify call data records associated with the received location data and to compare information in the received location data with corresponding information stored in the identified call data records to identify errors in the information stored in the planning repository.

Abstract: The disclosure relates to processing in-flight blocks in a processor pipeline according to an expected execution mode to reduce synchronization delays that could otherwise arise due to transitions among processor modes with varying privilege levels (e.g., user mode, supervisor mode, hypervisor mode, etc.). More particularly, a program counter associated with an instruction block to be fetched may be translated to one or more execute permissions associated with the instruction block and the instruction block may be associated with a speculative execution mode based at least in part on the one or more execute permissions. Accordingly, the instruction block may be processed relative to the speculative execution mode while in-flight within the processor pipeline.

Abstract: A system and method for batch sizing a formula that defining one or more hair dye materials and corresponding recommended amounts for creating an individual batch sized amount of a hair dye mixture. One method includes providing a control system having at least a processor and a computer-readable memory, wherein the memory contains software configured to receive a formula defining instructions for blending a hair dye mixture using one or more colorants and/or dye blending materials and amounts recommended for the hair dye mixture. The method further includes presenting a plurality of batch sizing adjustment criteria on a display; and receiving user input, via a user input device, selecting one or more of the plurality of batch sizing adjustment criteria. The batch sizing adjustment criteria includes service characteristics.

Abstract: A method is provided for preparing a hair dye color mixture. The method includes: providing a control system having at least a memory, input controls, and a display; storing in the memory at least one formula, the formula including one or more colorants and/or dye blending materials, and wherein each colorant and/or blending material is separately assigned to an initial product brand; receiving input from the input controls to change a colorant and/or blending material from the initial product brand to one or more subsequent product brands, and wherein the control system recalculates components of the formula using the one or more subsequent product brands in response to receiving input from the input controls; and matching the color of the hair dye color mixture made from colorants and/or dye blending materials of the initial product brand using colorants and/or dye blending materials of the one or more subsequent product brands, in response to the input.

Abstract: A spherical body inspection apparatus including a support arrangement realized to support a spherical body during an inspection procedure; a probe arrangement comprising a plurality of UT probes arranged about the spherical body such that the UT probes target a common test point at the surface of the spherical body; and a displacer for effecting at least one relative rotational displacement between the spherical body and the probe arrangement. Also described is a method of inspecting a spherical body.

Abstract: A prescription management system is used by an orthodontic or dental lab and a plurality of prescribing users who send prescriptions for customized orthodontic or dental appliances to the lab. The prescriptions are stored in a database selectively accessible by the lab and plurality of prescribing users. A digital workspace is provided in the system in which the lab or prescribing users may create designs for the customized appliances. The designs of the appliances are stored in the database. A tracking record of fabrication of the appliances is stored in the database. A plurality of billings are simultaneously generated in response to the submissions and storage of the prescriptions, the designs of the customized appliances and the fabrication of the designed customized appliances.

Abstract: An electrical connector assembly (1), comprising a housing (2) and an electrical connector receptacle (3) arranged to receive a complementary electrical connector, the housing arranged to be mounted to a support structure, the electrical connector receptacle arranged to be removably received within the housing, the electrical connector receptacle comprises a tongue (30) with a plurality of electrical contacts (31) arranged to connect with electrical contacts of the complementary electrical connector.

Abstract: A drive mechanism for a vacuum cleaner having a motor and an agitator includes a belt coupled to the motor and the agitator to drive the agitator, and a belt tensioner operable to selectively tension the belt. The belt tensioner includes an arm movable relative to the belt, a shaft coupled to the arm, a pulley rotatably coupled to the shaft, a bearing positioned substantially within the pulley and around a portion of the shaft, and a member fixed to the pulley to retain the bearing within the pulley.

Abstract: An apparatus for mapping an architectural register to a physical register can include a memory and control circuitry. The memory can be configured to store an intra-core register rename map and an inter-core register rename map. The intra-core register rename map can be configured to map the architectural register to the physical register of a core of a multi-core processor. The inter-core register rename map can be configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write according to program order. The control circuitry can be configured to maintain the intra-core register rename map and the inter-core register rename map.

Abstract: A proposed prefetcher may operate at a cache level where accesses are conducted using physical addresses. The proposed prefetcher may include one or more prefetch engines. Similar to conventional prefetchers, a prefetch engines of the proposed prefetcher may train on access patterns of a memory page to predict future accesses and perform prefetches based on the training. But unlike the conventional prefetchers, the trained prefetch engine may be reused for prefetching even when a request for a new page is received without requiring the prefetch engine to be newly trained on the new page. This can lower access latencies and lower cumulative training time.

Abstract: Performing distributed branch prediction using fused processor cores in processor-based systems is disclosed. In one aspect, a distributed branch predictor is provided as a plurality of processor cores supporting core fusion. Each processor core is configured to receive a program identifier from another of the processor cores (or from itself), generate a subsequent predicted program identifier, and forward the predicted program identifier (and, optionally, a global history indicator) to the appropriate processor core responsible for handling the next prediction. The processor core also fetches a header and/or one or more instructions for the received program identifier, and sends the header and/or the one or more instructions to the appropriate processor core for execution.

Abstract: Disclosed are methods and apparatuses for preventing memory violations. In an aspect, a fetch unit accesses, from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor, and fetches, from an instruction cache, the block of instructions. The processor executes load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.

Abstract: Providing memory dependence prediction in block-atomic dataflow architectures is disclosed. In one aspect, a memory dependence prediction circuit is provided. The memory dependence prediction circuit comprises a predictor table configured to store multiple predictor table entries, each comprising a store instruction identifier, a block reach set, and a load set. Using this data, the memory dependence prediction circuit determines, upon a fetch of an instruction block by an execution pipeline, whether the instruction block contains store instructions that reach dependent load instructions. If so, the store instructions are marked as having dependent load instructions to wake. In some aspects, the memory dependence prediction circuit is configured to determine whether the instruction block contains dependent load instructions reached by store instructions. If so, the memory dependence prediction circuit delays execution of the dependent load instructions.