Patents by Inventor Michel Harrand
Michel Harrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240054330Abstract: A computing circuit for computing a weighted sum of a set of first data using at least one parsimony management circuit includes a first buffer memory for storing all or some of the first data delivered sequentially and a second buffer memory for storing all or some of the second data delivered sequentially. The parsimony management circuit furthermore comprises a first processing circuit able: to analyze the first data in order to search for the first non-zero data and define a first skip indicator between two successive non-zero data, and to control the transfer, to the distribution circuit, of a first datum read from the first data buffer memory on the basis of the first skip indicator. The parsimony management circuit furthermore comprises a second processing circuit able to control the transfer, to the distribution circuit, of a second datum read from the second data buffer memory on the basis of the first skip indicator.Type: ApplicationFiled: December 15, 2021Publication date: February 15, 2024Inventor: Michel HARRAND
-
Publication number: 20220036169Abstract: A circuit for computing output data of a layer of an artificial neural network includes an external memory and an integrated system on chip comprising: a computing network comprising at least one set of at least one group of computing units; the computing network furthermore comprising a buffer memory connected to the computing unit; a weight-storing stage comprising a plurality of memories for storing the synaptic coefficients; each memory being connected to all the computing units of same rank; control means configured to distribute the input data such that each set of groups of computing units receives a column vector of the submatrix stored in the buffer memory implemented by one column. All the sets simultaneously receive column vectors that are shifted with respect to each other by a number of rows equal to a stride of the convolution operation.Type: ApplicationFiled: July 30, 2021Publication date: February 3, 2022Inventor: Michel HARRAND
-
Publication number: 20220036196Abstract: A computer for computing a layer (Ck, Ck+1) of an artificial neural network is provided. The computer is able to be configured in accordance with two separate configurations and comprises: a transmission line; a set of computing units; a set of weight memories each associated with a computing unit, each weight memory containing a subset of synaptic coefficients required and sufficient for the associated computing unit to carry out the computations necessary for either one of the two configurations and control means for configuring the computing units of the computer in accordance with either one of the two configurations. In the first configuration, the computing units are configured such that a weighted sum is computed in full by one and the same computing unit. In the second configuration, the computing units are configured such that a weighted sum is computed by a chain of multiple computing units arranged in series.Type: ApplicationFiled: July 30, 2021Publication date: February 3, 2022Inventor: Michel HARRAND
-
Patent number: 10559355Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.Type: GrantFiled: September 8, 2015Date of Patent: February 11, 2020Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Michel Harrand, Elisa Vianello, Olivier Thomas, Bastien Giraud
-
Patent number: 10540099Abstract: A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.Type: GrantFiled: December 12, 2014Date of Patent: January 21, 2020Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Michel Harrand, Elisa Vianello
-
Patent number: 10475509Abstract: A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.Type: GrantFiled: May 9, 2018Date of Patent: November 12, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVEInventors: Gabriel Molas, Michel Harrand, Elisa Vianello
-
Patent number: 10388376Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.Type: GrantFiled: May 9, 2018Date of Patent: August 20, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Gabriel Molas, Michel Harrand, Elisa Vianello, Cécile Nail
-
Patent number: 10235058Abstract: A system including: a memory including a plurality of pages; and a control circuit suitable for delivering user access to the memory and for implementing a balancing method for the wear of the memory, including movement of data within the memory, in which the control circuit is suitable for delivering, between the first and second consecutive page read or write operations of the wear balancing method and between the second and a third consecutive page read or write operation of the wear balancing method, one or more user accesses to the pages of the memory.Type: GrantFiled: December 12, 2014Date of Patent: March 19, 2019Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Michel Harrand, Elisa Vianello
-
Publication number: 20180330786Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Gabriel Molas, Michel Harrand, Elisa Vianello, Cécile Nail
-
Publication number: 20180330783Abstract: A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Gabriel MOLAS, Michel HARRAND, Elisa VIANELLO
-
Patent number: 9565122Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.Type: GrantFiled: October 9, 2012Date of Patent: February 7, 2017Assignee: KALRAYInventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin
-
Patent number: 9543012Abstract: A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.Type: GrantFiled: December 12, 2014Date of Patent: January 10, 2017Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventor: Michel Harrand
-
Publication number: 20160313930Abstract: A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.Type: ApplicationFiled: December 12, 2014Publication date: October 27, 2016Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Michel Harrand, Elisa Vianello
-
Publication number: 20160314837Abstract: A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.Type: ApplicationFiled: December 12, 2014Publication date: October 27, 2016Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventor: Michel HARRAND
-
Publication number: 20160313929Abstract: A system including: a memory including a plurality of pages; and a control circuit suitable for delivering user access to the memory and for implementing a balancing method for the wear of the memory, including movement of data within the memory, in which the control circuit is suitable for delivering, between the first and second consecutive page read or write operations of the wear balancing method and between the second and a third consecutive page read or write operation of the wear balancing method, one or more user accesses to the pages of the memory.Type: ApplicationFiled: December 12, 2014Publication date: October 27, 2016Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: Michel HARRAND, Elisa VIANELLO
-
Patent number: 9449688Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.Type: GrantFiled: September 8, 2015Date of Patent: September 20, 2016Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Olivier Thomas, Bastien Giraud, Michel Harrand, Elisa Vianello
-
Publication number: 20160071589Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.Type: ApplicationFiled: September 8, 2015Publication date: March 10, 2016Inventors: Olivier Thomas, Bastien Giraud, Michel Harrand, Elisa Vianello
-
Publication number: 20160071588Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.Type: ApplicationFiled: September 8, 2015Publication date: March 10, 2016Inventors: Michel Harrand, Elisa Vianello, Olivier Thomas, Bastien Giraud
-
Patent number: 9164807Abstract: A system including a plurality of processing units for executing tasks in parallel and a communication network. The processing units are organized into clusters of units, each cluster comprising a local memory. The system includes means for statically allocating tasks to each cluster of units, so that a task of an application is processed by the same cluster of units from one execution to another. Each cluster includes cluster management means for allocating tasks to each of its processing units and space in the local memory for executing them, so that a given task of an application may not be processed by the same processing unit from one execution to another. The cluster management means includes means for managing the tasks, means for managing the processing units, means for managing the local memory and means for managing the communications involving its processing units. The management means operate simultaneously and cooperatively.Type: GrantFiled: December 11, 2008Date of Patent: October 20, 2015Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Frédéric Blanc, Thierry Collette, Raphaël David, Vincent David, Michel Harrand, Stéphane Louise, Nicolas Ventroux
-
Patent number: 9064092Abstract: An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.Type: GrantFiled: August 10, 2012Date of Patent: June 23, 2015Assignee: KALRAYInventor: Michel Harrand