Abstract: A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address organized according to a hierarchical division defined by (@MSB, row address, column address), with @MSB identifying a particular module among the n modules. The circuit comprises first and second address buses, and first and second data buses used for reading and writing the modules, respectively. For each memory module, there is provided a multiplexer having two inputs connected to both address buses. The multiplexer output is connected to a row decoder and to first and second column decoders corresponding to the first and second data buses. Each multiplexer is controlled to allow writing and simultaneous reading of two distinct modules.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of said memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane to read words in a page of the memory and/or writing new words to a page of the memory and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory comprises an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.

Abstract: The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: A method and a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers. An access request including a page address, a column address, a write or read order, a possibly data to be written is received. The page address of the current request is compared with the page address of the preceding request and, if they are different, the controller stores the current request page in one non-used of the cache registers, preferably that which has not been used last.

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.

Abstract: A predictor provides as a pixel block of a current image a set of p target pixels of the preceding image so that each target pixel corresponds in the image to the adjacent pixels of the current pixel shifted by a predetermined motion vector. The predictor includes a search memory, each cell of which is independently addressable in read/write mode; three write decoders for simultaneously addressing in write mode three cells of three portions of the memory; p read decoders for simultaneously addressing in read mode p cells of p distinct sub-portions of the memory; and for controlling the write decoders so that p successive writings of data of the same nature corresponding to p adjacent points in the image are achieved in each of the p sub-portions.

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

Abstract: The present invention relates to a microprocessor including an operator dedicated to a concatenation of variable-length codes to form a sequence of contiguous codes, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word containing a group of bits and the second one of which indicates the length of the group of bits, the operator responding to the dedicated instruction by isolating, in the first parameter, the group of bits having the length indicated by the second parameter and by inserting the bit group so isolated into an active register, in concatenation with a bit group which has been inserted in the active register by a previous execution of the dedicated instruction.

Abstract: The present invention relates to a microprocessor including an operator dedicated to a signature calculation over a bit sequence, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word including a group of bits forming a successive portion of the sequence, and the second parameter of which indicates the length of the group of bits, the operator responding to the dedicated instruction by updating a signature register with a signature calculated over the content of the signature register and over the group of bits.

Abstract: The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.

Abstract: A matrix computation processor comprises a control unit and a data memory, and a plurality of computation units. The plurality of computation units are controlled by the control unit by means of a control bus comprising: a first group of wires connected to the plurality of computation units conveying a common instruction to the plurality of computation units; and a plurality of second groups of at least one wire, each being connected respectively to one of the plurality of computation units, conveying an instruction complement specific to each computation unit of the plurality of computation units.

Abstract: A dynamic memory includes a plurality of cells including capacitors connected by columns to bit lines and by rows to selection lines. An even row and an odd row contain reference cells, the cells of the other rows being memory cells. The capacitors of the reference cells have the same value as the capacitors of the memory cells. Means are also provided for, prior to reading a memory cell of an even row, connecting the selection line of the odd row of reference cells to an element having the same capacitance as a selection line, but which is precharged at the state opposite to the state of the selection line of the odd row of the reference cells.

Abstract: A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).