Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: The present invention is a managing system for managing a processing system of a substrate and it has an information accumulation section for accumulating information on the processing system, an information collecting unit for collecting the information from the information accumulation section, and a managing unit for obtaining the information in the information collecting unit via the Internet or an intranet to manage the processing system based on this information.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: The present invention is a managing system for managing a processing system of a substrate and it has an information accumulation section for accumulating information on the processing system, an information collecting unit for collecting the information from the information accumulation section, and a managing unit for obtaining the information in the information collecting unit via the Internet or an intranet to manage the processing system based on this information.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A radiographic intensifying screen set comprising a pair of a front intensifying screen and a rear intensifying screen, each comprising a support and a plurality of phosphor layers each having a binder resin and a phosphor dispersed therein, provided on the support, wherein at least some of the phosphor layers of the respective front intensifying screen and rear intensifying screen contain a fluorescent dye or a fluorescent pigment which absorbs some of emitted lights from the phosphors and emits lights having other wavelengths, the support for the front intensifying screen is a light-reflective support, and the support for the rear intensifying screen is a light-absorptive support.

Abstract: A resist pattern forming apparatus comprising a controller having a controlling portion that controls a processing of a coating and developing apparatus with a coating unit and a developing unit being provided therewith and an aligner being connected thereto, while an inspecting portion and the like measures at least one of a plurality of measurement items selected from, a reflection ratio and a film thickness of a base film and a resist film, a line width after the development, an accuracy that the base film matches with a resist pattern, a defect after the development, and so on. The measured data is transmitted to the controller. At the controller, a parameter subject to an amendment is selected based on the corresponding data of each of the measurement item such as the film thickness of the resist and the line width after the development, and the amendment of the parameters subject to the amendment is performed.

Abstract: The present invention provides a method for clone-multiplication of a Paphiopedilum wherein a scape terminal bud or an axillary shoot, whose surface has been sterilized, or an aseptic shoot obtained by an aseptic cultivation, of a Paphiopedilum stock, are cut into cross-sectional pieces which are then cultivated in a medium containing a plant hormone. By cutting an aseptic shoot containing a number of axillary buds into cross-sectional pieces and cultivating, a multishoot formation is feasible. Also by employing a liquid medium containing a solid support such as a rockwool or a paper filter in the culture, the plant death due to browning of tissues can effectively be prevented. In addition, by optimizing the method for sterilizing the buds before blooming, the medium composition and the culture condition, a large scale production of Paphiopedilums by means of a clone multiplication technology becomes feasible.

Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: One end of a flexible positioning cord is fixed on one end side of a molding drum and the positioning cord is then pulled from the other end side thereby applying a tension to the positioning cord. The tensed positioning cord presses a joint of an extensible fabric into one of tooth part forming grooves to position it therein. Next, a tension member cord is wound in a spiral form and the tension applied to the positioning cord is then relieved to allow the removal of the positioning cord from the tooth part forming groove. Thereafter, an unvulcanized rubber sheet is wrapped around the extensible fabric wound with the tension member cord, and the resultant substance is then subjected to cure through the application of pressure thereby forming a cylindrical slab. The slab is cut into round pieces at specific widths thereby obtaining synchronous belts.

Abstract: A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Abstract: A manufacturing method for polycarbonate comprising ?I! a process for manufacturing diaryl carbonate from an aromatic hydroxy compound and an aromatic hydroxy compound, ?II! a process for manufacturing polycarbonate by solution polymerization of the diaryl carbonate obtained in ?II! and an aromatic dihydroxy compound in the presence of a catalyst comprising a nitrogen-containing basic compound, and ?III! a process for separating and removing the nitrogen-containing compound from the aromatic hydroxy by-products in ?II! and returning the resultant aromatic hydroxy compounds to process ?I! effectively reuses aromatic hydroxy by-products (e.g., phenols) of polycarbonate manufacturing to manufacture diaryl carbonate, while suppressing the production of alkyl aromatic ethers and then uses this diaryl carbonate to manufacture polycarbonate with good productivity.

Abstract: A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.