Abstract: A memory device may include a controller and a plurality of flash memory dice. The controller is provided for read and write access and communications with a host. However, the controller may also be utilized to test one or more of the flash memory dice mounted on the device. In this way, testing may be achieved with a relatively modestly priced tester by making use of the capabilities of the onboard controller. As a result, the cost of a memory device may be reduced in some cases.

Abstract: A method and apparatus for synchronizing a micro controller in a flash memory device. An interface circuit receives a user command over a host bus. A synchronizer circuit enables an oscillator circuit if the user command specifies an operation on a flash cell array. The oscillator circuit generates a clock signal for synchronizing the micro controller. After completion of the program or erase operation, the synchronizer circuit disables the oscillator circuit if a subsequent user command that specifies another program or erase operation for the micro controller is not pending.

Abstract: Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.

Abstract: A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Abstract: A flash memory device having a page buffer circuit providing a shared resource between a flash array controller circuit and a user. The page buffer circuit comprises a Plane A and a Plane B, wherein each of the planes A and B is a static random access memory array. The page buffer circuit further comprises a mode control circuit for enabling access to the planes A and B over a host bus in a user mode and access to the planes A and B by the flash array controller in a flash array controller mode.

Abstract: A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus.

Abstract: A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.

Abstract: A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Abstract: A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block.

Abstract: Circuitry for reconfiguring a pin of an integrated circuit. The reconfiguration circuitry includes a multiplexer, whose output is coupled to the pin. Upon powering-up the integrated circuit, the multiplexer couples to the pin to a first signal that conforms to the historical definition of the pin's function. The user reconfigures the pin by issuing a command that causes the multiplexer to couple a second signal to the pin. This second signal behaves in a manner more useful to the user. The switch from the first signal to the second is achieved via a reconfiguration register, which generates the multiplexer's select signal. A control engine within the integrated circuit responds to the reconfiguration command by writing once to the reconfiguration register. The pin remains reconfigured until the integrated device is powered down.

Abstract: A method of, and apparatus for, storing and prioritizing among erase block and program word commands is described for a nonvolatile memory device. This prevents the depth of an operation queue responsible for queuing program and erase commands from limiting the number of erase commands that are stored at one time. The first erase command received serves as a place holder, holding a place within the operation queue for all subsequently received erase commands. All subsequently received erase commands are absorbed and cleared from the operation queue. As a result, the operation queue may receive additional commands and an erase command may be queued for every block of memory within the nonvolatile memory device. Absorbed erase commands can be prioritized in response to subsequently received program commands. Blocks are flagged for priority erasure using a priority register. Additionally, interrupt windows located at safe points permit interruption of erase operations to handle command interrupts.

Abstract: A circuit for selectively protecting data stored within a range of addresses from programming and erasing. The circuit includes a circuit for generating an active lock signal. The circuit generates an active lock signal when a protect signal is active and an address signal represents an address within the protected range. Both erasure and programming are prevented while the lock signal is active. Programming and erasure of protected data is permitted while the lock signal is inactive. A method for selectively protecting data within a range of addresses on a non-volatile semiconductor memory from programming or erasure is also described.

Abstract: A method of preconditioning a nonvolatile memory array including a first memory cell and a second memory cell. Preconditioning begins by applying an initial precondition pulse to all memory cells in the nonvolatile memory array without pausing to perform precondition verification. After this first step, precondition verification begins. The voltage level of the first memory cell is sensed and compared to a selected voltage level. If the threshold voltage of the first memory cell is below the selected voltage, the first memory cell did not precondition verify. In that case, another precondition pulse is then applied to the first memory cell. Application of precondition pulses and precondition verification continues until the first memory cell verifies as preconditioned. Attention turns to the second memory cell after the first memory cell precondition verifies. If the second memory cell does not precondition verify another precondition pulse is applied to the second memory cell.

Abstract: A method of increasing the data throughput of a memory device including a page buffer. Data throughput is increased by pipelining write operations such that one plane of the page buffer is being used to program the memory array of the device while the other plane of the page buffer is being loaded with data to be used in the next program operation. The first write operation is set up by loading a first block of data in to the first plane of the page buffer. In the following clock cycle, the first operation begins by commanding the memory device to program the memory array with the first block of data stored in the first plane. The second write operation is setup immediately following the first command to program. The second write operation is setup by loading a second block of data into the second plane of the page buffer. Loading of the second plane occurs while the memory array is being programmed from the first plane.

Abstract: Circuitry for programming a non-volatile semiconductor memory is described. The circuitry includes a circuit for enabling the non-volatile semiconductor memory to program a bit of the non-volatile semiconductor memory. The enabling circuit causes the bit to be programmed according to a pattern bit. The circuitry also includes a second enabling circuit, which enables the non-volatile semiconductor memory to verify the programming of the bit. Circuitry for erasing a non-volatile semiconductor memory is disclosed. A method for programming a nonvolatile semiconductor memory is also described.

Abstract: A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state.

Abstract: A flash memory system includes a user interface and array controller. The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution. The user interface further functions as an arbiter to control the priority of commands to be executed. The array controller performs the operations on the flash array such as program and erase. The array controller consists of a general purpose processor with program memory which is programmable by the user. The program memory stores one or more algorithms that can be executed by the array controller. The algorithm is selected according to the command received at the user interface. The algorithms can be customized simply by programming the program memory. The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command.

Abstract: A command state machine for control circuitry associated with a memory array which control circuitry includes apparatus for programming and erasing the memory array including first state machine logic apparatus for providing control signals for reading the memory array and for initiating operations of the apparatus for programming and erasing the memory array in response to commands, and second state machine logic apparatus for controlling information derived from the memory array, the first and second state machine logic apparatus being adapted to assume predetermined states in response to any invalid command which have no adverse affect on the memory array or the control circuitry.

Abstract: Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state.

Abstract: In a memory array having a plurality of rows and columns of memory devices for storing binary conditions, apparatus for selecting particular memory devices, a sense amplifier for transferring indications of the conditions of selected memory devices, and apparatus for generating signals indicative of conditions other than the state of the memory devices, the improvement including a multiplexor, the multiplexor being arranged to accept as input the output of the sense amplifier and the signals indicative of conditions other than the state of the memory devices, the multiplexor and the apparatus for generating signals indicative of conditions other than the state of the memory devices being positioned in a manner that parasitic capacitance affecting the input to the sense amplifier is not created. The output of the sense amplifier may also be connected to other internal circuits so that the memory array may be accessed while bringing other signals to the output pins.