Abstract: Override control circuitry and a method for terminating a sequence for erasing or programming a computer memory are described. A command register is provided for storing a command sent by an external processor to the memory. A decoder circuit decodes the command and outputs an erase or program set-up signal if the command indicates the initiation of an erase or program sequence. A latch is coupled to the decode circuit for storing the erase or program set-up signal. An override timer is located between the latch and the memory. The override timer includes a counter which is initialized and begins counting when the erase or program set-up signal is latched. The override timer also includes a circuit that detects when the counter has reached a first count for an erase sequence and a second count for a program sequence. The circuit then generates an erase or program override signal. An erase switch detects the erase override signal and prevents the application of an erase voltage to the memory.

Abstract: A method of determining erasure characteristics of a nonvolatile semiconductor memory array using an on-board write state machine is described. The method begins by configuring the write state machine to apply a single erase pulse to the array and then issuing an erase command. If array erasure is unsuccessful, another erase command is issued. Erase commands are reissued until every address within the array is successfully erased.

Abstract: A status register in a non-volatile semiconductor memory is described. The status register outputs to pins of the non-volatile semiconductor memory a number of signals that indicate the status of program and erase operations performed on the memory array of the non-volatile semiconductor memory. The status register includes a clock circuit that generates a clock signal in response to an output enable signal. The clock signal is coupled to a pair of latches that respond by coupling their signals to the pins. One latch couples an erase fail signal to a pin to indicate whether the memory array has been sucessfully erased. The other latch couples a program fail signal to a pin to indicate whether an addressed memory cell of the memory array has been sucessfully programmed.

Abstract: A testing apparatus for testing connectivity to a circuit board of an integrated circuit chip disposed on the circuit board. The circuit board has signal transmission circuitry. The integrated circuit chip has pins coupled to the signal transmission circuitry. The pins are for receiving digital signals asserted external to the chip. Each digital signal has a binary value depending upon whether the signal is asserted or not. The testing apparatus tests connectivity of the pins. The testing apparatus has signal assertion and reception circuitry that is coupled to the signal transmission circuitry of the circuit board but is not disposed on the chip. Command sensing, pin state storage, general storage, algorithm execution and general data output circuitry are all disposed on the chip to be tested. The command sensing circuitry is for sensing external assertion of a test command by the signal assertion and reception circuitry. The test command causes the chip to enter a test mode.

Abstract: Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned.

Abstract: A method is described for verifying the operation of next state logic within a write state machine for automatically programming and erasing a flash memory. Verification of the next state logic's operation begins by configuring the write state machine in a test mode. Afterward, the next state logic is cycled through its possible output states by providing the next state logic with all possible input states. Outputs from next state logic are compared to expected outputs, thereby verifying the operation of the next state logic. Also described is circuitry for verifying the operation of next state logic within a write state machine. The circuitry includes test registers for storing test signals. In response to the test signals a first means isolates the next state logic from the write state machine. A second means provides alternative inputs to the next state logic in response to the test signals.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: Circuitry for suspending an automated sequence for a nonvolatile semiconductor memory is described. The circuitry and memory reside on the same substrate. The circuitry includes a circuit for suspending erasure at a predetermined state of the erase sequence when a suspend signal is active and a circuit for resuming erasure at a predetermined state of the erase sequence when the suspend signal goes inactive. A method for suspending automated erasure sequence of a non-volatile semiconductor memory is also described. A suspend signal is received and erasure is suspended after a first erasure step of the erase sequence if suspend signal is active. Erasure resumes at a second erasure step of the erase sequence when the suspend signal goes inactive.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.

Abstract: An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and output terminals; the output terminals of each of the latches being connected to individual portions of the digital circuitry to effect an individual operation thereby; apparatus connected to the input terminals of the latches for setting individual selected ones of the latches to provide selected test conditions; and apparatus for transferring the condition of a selected number of the latches simultaneously to effect a selected test condition.

Abstract: Circuitry for handshaking between a command state machine and write state machine is described. The handshaking circuitry, the command state machine and the write state machine are part of a non-volatile semiconductor memory device that includes a memory array. The command state machine receives commands from a user and communicates valid commands to the write state machine, which responds by performing automated program and erasure operations on the memory array, as appropriate. The command state machine identifies valid commands based upon signals generated by the handshaking circuitry. The handshaking circuitry includes three latches, an OR gate and a NAND gate. The serially coupled latches store an idle signal from the write state machine. The OR gate is coupled to outputs from the second and third of the serially coupled latches and generates a signal indicative of the whether the write state machine is idle.

Abstract: Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure.

Abstract: Circuitry for discharging a drain of a cell of a non-volatile semiconductor memory is described. A discharge transistor is coupled between (1) the drain of the cell and (2) ground for selectably (a) providing a discharge paths to ground for the drain of the cell when the discharge transistor is enabled and (b) not providing a discharge path to ground for the drain of the cell when the discharge transistor is not enabled. Circuitry is coupled to the discharge transistor for enabling the discharge transistor for a duration that both begins and ends (1) after a first operation is performed with respect to the cell and (2) before a verify operation is performed with respect to the cell.

Abstract: A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.

Abstract: A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.