Abstract: A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A semiconductor device that transmits data in wide bus width regardless of the width of an external data bus connected thereto. On the device's data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L=m/n bits. An output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. A data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.

Abstract: A memory cell matrix with a plurality of associative memory cells and match lines are respectively divided into two in the direction of the match line. A first memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the first memory cell matrix, and a match line sense amplifier that detects the potential of the match line. A second memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the second memory cell matrix, a match line sense amplifier that detects the potential of the match line in the second memory cell matrix, and a second match line control circuit. The second match line control circuit operates the match line pre-charge circuit in the second memory cell matrix, to pre-charge the match line, only when the data comparison result in the first memory cell matrix indicates agreement.

Abstract: A memory cell matrix with a plurality of associative memory cells and match lines are respectively divided into two in the direction of the match line. A first memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the first memory cell matrix, and a match line sense amplifier that detects the potential of the match line. A second memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the second memory cell matrix, a match line sense amplifier that detects the potential of the match line in the second memory cell matrix, and a second match line control circuit. The second match line control circuit operates the match line pre-charge circuit in the second memory cell matrix, to pre-charge the match line, only when the data comparison result in the first memory cell matrix indicates agreement.

Abstract: A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.

Abstract: A contents addressable memory comprises: memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; and search buses extending along the column and match lines extending along the row; and a comparison circuit, provided in each memory cell, comparing data in search bus and data stored in memory cell and outputting comparison result to the match line. Transfer units having a first transfer gate, a transfer cell for temporarily storing data from memory cell, and a second transfer gate are provided between a pair of memory cells arranged along the column. Data from one of pair of memory cells is stored in the transfer cell via first or second transfer gate, then that data stored in transfer cell is stored in other of pair of memory cells via the second or first transfer gate.

Abstract: A content addressable memory device includes a match line having a potential thereof changed according to whether data of a memory cell matches a search key of a search bus, a precharge circuit which precharges the match line, a sample-&-hold circuit which samples and holds the potential of the match line, and a detection circuit which detects the potential held by the sample-&-hold circuit.

Abstract: A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.

Abstract: A content addressable memory device includes a first match line which is a first one of two portions into which a whole match line corresponding to a single item of entry data is divided, and changes from a first potential to a second potential when corresponding entry data does not match an entry key, a second match line which is a second one of the two portions into which the whole match line corresponding to the single item of entry data is divided, and changes from a second potential to a first potential when corresponding entry data does not match an entry key, a first precharge circuit which precharges the first match line to the first potential, a second precharge circuit which precharges the second match line to the second potential, and a short-circuiting circuit which short-circuits the first match line and the second match line with each other prior to precharging by the first and second precharge circuits if both of the first and second match lines indicate a mismatch.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line.

Abstract: A contents addressable memory comprises: memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; and search buses extending along the column and match lines extending along the row; and a comparison circuit, provided in each memory cell, comparing data in search bus and data stored in memory cell and outputting comparison result to the match line. Transfer units having a first transfer gate, a transfer cell for temporarily storing data from memory cell, and a second transfer gate are provided between a pair of memory cells arranged along the column. Data from one of pair of memory cells is stored in the transfer cell via first or second transfer gate, then that data stored in transfer cell is stored in other of pair of memory cells via the second or first transfer gate.

Abstract: A content addressable memory device includes a first match line which is a first one of two portions into which a whole match line corresponding to a single item of entry data is divided, and changes from a first potential to a second potential when corresponding entry data does not match an entry key, a second match line which is a second one of the two portions into which the whole match line corresponding to the single item of entry data is divided, and changes from a second potential to a first potential when corresponding entry data does not match an entry key, a first precharge circuit which precharges the first match line to the first potential, a second precharge circuit which precharges the second match line to the second potential, and a short-circuiting circuit which short-circuits the first match line and the second match line with each other prior to precharging by the first and second precharge circuits if both of the first and second match lines indicate a mismatch.

Abstract: A content addressable memory device includes a match line having a potential thereof changed according to whether data of a memory cell matches a search key of a search bus, a precharge circuit which precharges the match line, a sample-&-hold circuit which samples and holds the potential of the match line, and a detection circuit which detects the potential held by the sample-&-hold circuit.

Abstract: According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A memory controller for controlling a memory that is connected thereto and outputs data of a double data rate together with a strobe signal includes a clock signal generation circuit which generates a clock signal supplied to the memory, and a data acquisition circuit which delays the strobe signal through feedback control that makes a delay substantially equal to a ¼ cycle of the clock signal, and which latches the data in response to a timing signal that is the delayed strobe signal.