Abstract: A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A memory controller for controlling a memory that is connected thereto and outputs data of a double data rate together with a strobe signal includes a clock signal generation circuit which generates a clock signal supplied to the memory, and a data acquisition circuit which delays the strobe signal through feedback control that makes a delay substantially equal to a ¼ cycle of the clock signal, and which latches the data in response to a timing signal that is the delayed strobe signal.

Abstract: According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A semiconductor device consuming a first voltage includes a voltage-detection circuit which detects a voltage level of the first voltage, and a control circuit which controls the voltage-detection circuit to operate for a predetermined time period in accordance with a timing at which the first voltage is started to be consumed.

Abstract: A semiconductor device operates in one of at least two different modes including a first mode and a second mode. The semiconductor device includes a first voltage generating circuit operating in the first mode and the second mode and having a power to supply a first amount of current in order to generate a predetermined voltage level, and a second voltage generating circuit operating only in the second mode and having a power to supply a second amount of current greater than the first amount of current in order to generate the predetermined voltage level, wherein the first voltage generating circuit increases the first amount of current in the second mode compared to in the first mode.