Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract: The present invention relates to a semi-aromatic polyamide and a method for preparing it with low wastewater discharge. The semi-aromatic polyamide for the present invention is obtained by introducing aromatic dicarboxylic acid, aliphatic diamine containing 4˜14 carbon atoms and the wastewater generated during the previous prepolymerization into an autoclave for prepolymerization reaction and then further polymerizing the prepolymer. In this preparation method, the wastewater generated during polymerization is recycled, thus greatly reducing the wastewater discharge; the raw materials in the wastewater are effectively recycled, thus improving the utilization rate of raw materials; meanwhile, the diamine in the wastewater compensates that lost along with water discharge during prepolymerization, thus ensuring the Mole ratio balance between dicarboxylic acid monomer and diamine monomer.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract: A method and apparatus is disclosed whereby the scheduling of network transmissions in a wireless backhaul network is determined using a cross-layer optimization algorithm. In a first embodiment, the algorithm assumes a good MAC layer transmit schedule has been provided and computes optimal network layer routes as well as transmit beam patterns and transmit powers in a semi-distributed manner. According to this embodiment, the optimization goal is the throughput from each access point, or node in the network, to the core network. In another embodiment, an independent set of transmitting nodes is determined at the MAC layer in a way such that no link in the set interferes with another link and no link is scheduled to transmit and receive at the same time. According to this embodiment, a column generation algorithm is used to find a maximal weighted independent set and to achieve optimal network transmission throughput.

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: The present disclosure provides a method of forming a photomask layout. In one example, the method comprises selecting a pattern feature on the photomask layout, defining a global area centered at the pattern feature on the photomask layout, calculating a pattern density inside the global area, and correcting the pattern feature based on the pattern density and patterning process data.

Abstract: A method and apparatus is disclosed whereby the scheduling of network transmissions in a wireless backhaul network is determined using a cross-layer optimization algorithm. In a first embodiment, the algorithm assumes a good MAC layer transmit schedule has been provided and computes optimal network layer routes as well as transmit beam patterns and transmit powers in a semi-distributed manner. According to this embodiment, the optimization goal is the throughput from each access point, or node in the network, to the core network. In another embodiment, an independent set of transmitting nodes is determined at the MAC layer in a way such that no link in the set interferes with another link and no link is scheduled to transmit and receive at the same time. According to this embodiment, a column generation algorithm is used to find a maximal weighted independent set and to achieve optimal network transmission throughput.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: The present disclosure provide a method of forming a photomask layout. In one example, the method comprises selecting a pattern feature on the photomask layout, defining a global area centered at the pattern feature on the photomask layout, calculating a pattern density inside the global area, and correcting the pattern feature based on the pattern density and patterning process data.

Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.

Abstract: An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an Mtop solid conductive plate, and an Mtop?1 solid conductive plate. The Mtop solid conductive plate is located under the bond pad. The Mtop plate is electrically coupled to the bond pad. The Mtop?1 solid conductive plate is located under the Mtop plate. A low-k dielectric layer is located under the bond pad of the bond pad structure. At least part of an active circuit is located under the bond pad of the bond pad structure.

Abstract: An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.