Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: Display of an interpolated or extrapolated video unit, such as a video frame, may be selectively enabled based on a quality analysis. This disclosure also describes selection of reference video frames to be used for interpolation or extrapolation. A decoder may apply a quality-focused mode to select a reference frame based on quality criteria. The quality criteria may indicate a level of quality likely to be produced by a reference frame. If no reference frames satisfy the quality criteria, interpolation or extrapolation may be disabled. A decoder may apply a resource-focused frame interpolation mode to enable or disable frame interpolation or extrapolation for some frames based on power and quality considerations. In one mode, frame interpolation may be disabled to conserve power when reference frames are not likely to produce satisfactory quality. In another mode, the threshold may be adjustable as a function of power saving requirements of the decoder.

Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

Abstract: A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Abstract: Embodiments of the present invention relate to methods, systems, a machine-readable medium operable in a controller, and apparatus for controlling a multi-phase inverter that drives a multi-phase electric machine. When a sensor fault is detected, a phase current angle is computed based on the feedback stator currents, and used to estimate an angular velocity and an angular position of a rotor of the multi-phase electric machine. When the estimated angular velocity of the multi-phase electric machine is less than a transition angular velocity threshold, an open-circuit response can be applied at the multi-phase inverter by controlling all switches in the multi-phase inverter drive to be open. By contrast, when the estimated angular velocity is greater than the transition angular velocity threshold, a short-circuit response can be applied at the multi-phase inverter by controlling selected switches in the multi-phase inverter drive to connect all phases of the multi-phase inverter to a single bus (e.g.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract: Methods and apparatus are provided for rotor and stator temperature compensation for field weakening current. The method comprises generating a phase voltage feed back signal Vph based in part on pre-defined optimal current commands (ID* and IQ*) received by the IPM, generating a phase voltage command (Vphcmd) based in part on a temperature of a magnetic rotor and stator of the IPM, and generating a phase voltage error (Verror) by subtracting the phase voltage feed back signal (Vph) from the phase voltage command (Vphcmd). The method further comprises generating a d-axis command current correction value (?Id) and a q-axis command current correction value (?Iq) from the phase voltage error (Verror); and adjusting the pre-defined optimal current commands (ID* and IQ*) by the d-axis and the q-axis command current correction values (?Id and ?Iq).

Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract: The techniques of the disclosure are directed to reducing power consumption in a device through adaptive backlight level (ABL) scaling. The techniques may utilize a temporal approach in implementing the ABL scaling to adjust the backlight level of a display for a current video frame in a sequence of video frames presented on the display. The techniques may include receiving an initial backlight level adjustment for the current video frame and determining whether to adjust the backlight level adjustment for the current video frame based on a historical trend. The techniques may also determine the historical trend of backlight level adjustments between the current video frame and one or more preceding video frames in the sequence.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity.

Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

Abstract: Embodiments of the present invention relate to methods, systems, a machine-readable medium operable in a controller, and apparatus for controlling a multi-phase inverter that drives a multi-phase electric machine. When a sensor fault is detected, a phase current angle is computed based on the feedback stator currents, and used to estimate an angular velocity and an angular position of a rotor of the multi-phase electric machine. When the estimated angular velocity of the multi-phase electric machine is less than a transition angular velocity threshold, an open-circuit response can be applied at the multi-phase inverter by controlling all switches in the multi-phase inverter drive to be open. By contrast, when the estimated angular velocity is greater than the transition angular velocity threshold, a short-circuit response can be applied at the multi-phase inverter by controlling selected switches in the multi-phase inverter drive to connect all phases of the multi-phase inverter to a single bus (e.g.