Patents by Inventor Min Yang

Min Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088553
    Abstract: The present invention relates to a signal shielding apparatus and an antenna apparatus including same, and in particular, comprises a shield cover which is stacked and disposed on a printed board assembly (hereinafter, abbreviated to “PBA”), in which a plurality of signal-related components are mounted on one side thereof to prevent leakage of a signal from the plurality of signal-related components, wherein a grooved shield cover seating groove is formed in one surface of the PBA, and an insertion end insertably seated in the shield cover seating groove is integrally formed in the other surface from among one surface and the other surface of the shield cover, the other surface facing the one surface of the PBA, thereby providing advantages in that an increase in the manufacturing cost may be prevented, EMI shielding may be facilitated, and heat dissipation performance may be significantly improved.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Applicant: KMW INC.
    Inventors: Duk Yong KIM, Bae Mook JEONG, Kyo Sung JI, Chi Back RYU, Won Jun PARK, Jun Woo YANG, Seong Min AHN, Ki Hun PARK, Jae Eun KIM
  • Publication number: 20240088197
    Abstract: A light emitting chip including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a first bonding layer interposed between the first and second LED sub-units, a second bonding layer interposed between second and third LED sub-units, and a first connection electrode electrically connected to and overlapping at least one of the first, second, and third LED sub-units, the first connection electrode having first and second opposing side surfaces, the first side surface having a first length and the second side surface having a second length, in which the difference in length between the first side surface and the second side surface of the first connection electrode is greater than a thickness of at least one of the LED sub-units.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Jong Min JANG, Chang Yeon KIM, Myoung Hak YANG
  • Patent number: 11926922
    Abstract: The embodiments of the present disclosure disclose a method and an apparatus for crystal growth. The method for crystal growth may include: placing a seed crystal and a target source material in a growth chamber of an apparatus for crystal growth; executing a growth of a crystal based on the seed crystal and the target source material according to physical vapor transport; determining whether a preset condition is satisfied during the crystal growth process; and in response to determining that the preset condition is satisfied, replacing a sublimated target source material with a candidate source material. In the present disclosure, by replacing the sublimated target source material with the candidate source material, a crystal with large-size and high-quality can be grown.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 12, 2024
    Assignee: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu Wang, Tian Yang, Zhenxing Liang, Min Li
  • Publication number: 20240081061
    Abstract: A volatile memory device and a nonvolatile memory device are provided. Provided is a plurality of gate electrodes and a plurality of insulating patterns alternately stacked on top of each other in a first direction, an information storage film formed along a sidewall of a trench, wherein the trench extends through the plurality of gate electrodes and the insulating patterns in the first direction, and a semiconductor pattern formed on the information storage film, wherein the semiconductor pattern is made of polycrystalline silicon composed of a first monocrystalline silicon and a second monocrystalline silicon, wherein a metal silicide is present in a grain boundary between the first monocrystalline silicon and the second monocrystalline silicon, wherein the metal silicide is absent in each of the first monocrystalline silicon and the second monocrystalline silicon except for the grain boundary therebetween.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventors: Yu Yeon KIM, Si Yeong YANG, Chae Ho KIM, Kwang Min PARK
  • Patent number: 11923032
    Abstract: The present disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first and a second coupling capacitor. A first terminals of the first and second coupling capacitors are connected to a first word line and a second word line, respectively. The first terminals of the first and second coupling capacitors are also connected to a first and a second voltage supply, respectively. The circuit further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send alarm signal when a differential voltage between the first input and the second input of the comparator is larger than a hysteresis level of the comparator.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Kun Yang, Min She, Albert I. Ming Chang
  • Patent number: 11922963
    Abstract: Systems and methods are provided for generating and operating a speech enhancement model optimized for generating noise-suppressed speech outputs for improved human listening and live captioning. A computing system obtains a speech enhancement model trained on a first training dataset to generate noise-suppressed speech outputs and an automatic speech recognition model trained on a second training dataset to generate transcription labels for spoken language utterances. A third training dataset comprising a set of spoken language utterances is applied to the speech enhancement model to obtain a first noise-suppressed speech output which is applied to the automatic speech recognition model to generate a noise-suppressed transcription output for the set of spoken language utterances.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 5, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xiaofei Wang, Sefik Emre Eskimez, Min Tang, Hemin Yang, Zirun Zhu, Zhuo Chen, Huaming Wang, Takuya Yoshioka
  • Patent number: 11923567
    Abstract: The present invention relates to a battery cell for evaluating an internal short circuit, and a method for evaluating using the battery cell, wherein an internal short circuit state of a battery cell can be easily induced and, at the same time, an effective internal short circuit evaluation is possible, and the battery cell comprising: first and second electrodes which comprise a coated region on which an electrode mixture layer is coated on a metal current collector and a non-coated region on which an electrode mixture layer is not coated, and which comprise first and second electrode tabs which protrude in one direction from the coated region and do not have an electrode mixture layer coated thereon.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 5, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Sol Nip Lee, Jeong Min Yang
  • Patent number: 11923456
    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
  • Publication number: 20240074180
    Abstract: A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shasha LIU, Tianhui ZHANG, Min YANG, Xiaoming MAO, Zongliang HUO
  • Publication number: 20240072158
    Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
  • Publication number: 20240066808
    Abstract: A 3-dimensional (3D) printing device using a support body composition including a curing agent includes a support body, a structure body, and a controller, in which the support body composition includes a curing agent configured to cure the structure body.
    Type: Application
    Filed: November 26, 2021
    Publication date: February 29, 2024
    Inventors: Hyung Sun YOON, Young Hoon ROH, Young Min KIM, Kyung Jik YANG
  • Publication number: 20240069689
    Abstract: A method of supporting divided screen areas and a mobile terminal employing the same are disclosed. The method includes: generating input signals for one of sequentially and simultaneously activating a plurality of user functions; activating the user functions according to generated input signals; dividing a screen into divided screen areas that correspond to activated user functions; and outputting functional view areas associated with the activated user functions to the corresponding divided screen areas.
    Type: Application
    Filed: September 20, 2023
    Publication date: February 29, 2024
    Inventors: Hyung Min YOOK, Sung Sik YOO, Kang Won LEE, Myeong Lo LEE, Young Ae KANG, Hui Chul YANG, Yong Ki MIN
  • Publication number: 20240068000
    Abstract: The present invention relates to an E. coli hisG-derived ATP-phosphoribosyltransferase variant having a reduced feedback inhibition by histidine and a strain expressing the same. The variant may maintain its activity even at a high histidine concentration, thus increasing histidine production.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 29, 2024
    Applicant: DAESANG CORPORATION
    Inventors: Jong Yun HAN, Chel Min YANG, Yong Soo KIM, Young Il JO
  • Patent number: 11912933
    Abstract: The invention provides a suspension modifier directly added into fracturing fluid for real-time proppant modification during fracturing and the application thereof, relating to the field of oil and gas production technologies. The suspension modifier is a controlled release nanoemulsion and comprises surface hydrophobic modifier, surfactant, cosurfactant and water. The suspension modifier is directly added into clear-water or active-water fracturing fluid while the proppant is added into water. After stirring, the suspension modifier is capable of self-assembling and being adsorbed on the proppant surface, so that the proppant surface becomes hydrophobic and aerophilic. The invention no longer requires the proppant to be pretreated, and the bubble-suspended proppant can be obtained directly by adding the suspension modifier to the clear-water or active-water fracturing fluid, and meanwhile adding the proppant to the fracturing fluid.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: February 27, 2024
    Assignee: Chengdu University of Technology
    Inventors: Bo Yang, Yu Liu, Hao Zhang, Di Yang, Min Ren, Yang Yang, Ying Zhong, Bin Yang, Jiping She
  • Patent number: 11915853
    Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Mo Lim, Seung Min Lee, Byeong Cheol Moon, Yong Hui Li, Byung Soo Kang, Ju Hwan Yang, Tai Yon Cho, No Il Park, Tae Jun Choi
  • Patent number: 11917830
    Abstract: A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 27, 2024
    Assignee: XIANGTAN UNIVERSITY
    Inventors: Min Liao, Siwei Dai, Yanwei Huan, Qijun Yang, Zhaotong Liu, Yichun Zhou
  • Patent number: 11916172
    Abstract: An epitaxial structure adapted to a semiconductor pickup element is provided. The semiconductor pickup element has at least one guiding structure and provided with a pickup portion. The epitaxial structure includes a semiconductor layer corresponding to the pickup portion and capable of being picked up by the semiconductor pickup element. The epitaxial structure also includes at least one alignment structure disposed on the semiconductor layer and corresponding to the at least one guiding structure, so that the epitaxial structure and the semiconductor pickup element are positioned relative to each other. The number of the at least one alignment structure matches the number of the at least one guiding structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 27, 2024
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Shiang-Ning Yang, Yi-Min Su, Yu-Yun Lo, Bo-Wei Wu, Tzu-Yu Ting
  • Publication number: 20240060103
    Abstract: The present invention relates to an E. coli hisG-derived ATP-phosphoribosyltransferase variant having a reduced feedback inhibition by histidine and a strain expressing the same. The variant may maintain its activity even at a high histidine concentration, thus increasing histidine production.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 22, 2024
    Applicant: DAESANG CORPORATION
    Inventors: Jong Yun HAN, Chel Min YANG, Yong Soo KIM, Young Il JO
  • Publication number: 20240060057
    Abstract: The present invention relates to an E. coli hisG-derived ATP-phosphoribosyltransferase variant having a reduced feedback inhibition by histidine and a strain expressing the same. The variant may maintain its activity even at a high histidine concentration, thus increasing histidine production.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 22, 2024
    Applicant: DAESANG CORPORATION
    Inventors: Jong Yun HAN, Chel Min YANG, Yong Soo KIM, Young Il JO
  • Publication number: 20240060104
    Abstract: The present invention relates to an E. coli hisG-derived ATP-phosphoribosyltransferase variant having a reduced feedback inhibition by histidine and a strain expressing the same. The variant may maintain its activity even at a high histidine concentration, thus increasing histidine production.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 22, 2024
    Applicant: DAESANG CORPORATION
    Inventors: Jong Yun HAN, Chel Min YANG, Yong Soo KIM, Young Il JO