Patents by Inventor Ming-Chen Lu
Ming-Chen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11062969Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.Type: GrantFiled: January 29, 2019Date of Patent: July 13, 2021Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
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Patent number: 10504823Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.Type: GrantFiled: March 14, 2017Date of Patent: December 10, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Hongtao Gao, Jun Lu, Ming-Chen Lu, Jianxin Ye, Yan Huo, Hua Pan
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Publication number: 20190157174Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.Type: ApplicationFiled: January 29, 2019Publication date: May 23, 2019Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
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Patent number: 10242926Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.Type: GrantFiled: June 29, 2016Date of Patent: March 26, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
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Publication number: 20180254316Abstract: The invention provides a manufacturing method of a metal-insulator-metal device, including: forming a first metal layer, an insulation layer, and a second metal layer sequentially on a base to form a metal-insulator-metal structure; forming a patterned mask layer on at least a portion of the second metal layer, etching the second metal layer and the insulation layer on which the patterned mask layer is not formed using an etchant without carbon; and cleaning the etched metal-insulator-metal structure using a mixed solution containing oxidants and metal oxide etchants to remove excess polymer remaining on the metal-insulator-metal structure.Type: ApplicationFiled: June 14, 2017Publication date: September 6, 2018Applicant: Powerchip Technology CorporationInventors: Hsin Tai, Po-Cheng Chang, Hui-Chin Huang, Pei-Ting Tou, Ming-Chen Lu
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Patent number: 10043736Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.Type: GrantFiled: July 7, 2016Date of Patent: August 7, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
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Publication number: 20180005912Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
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Patent number: 9854686Abstract: A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad.Type: GrantFiled: March 13, 2015Date of Patent: December 26, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
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Publication number: 20170186675Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Hongtao Gao, Jun Lu, Ming-Chen Lu, Jianxin Ye, Yan Huo, Hua Pan
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Patent number: 9685430Abstract: A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.Type: GrantFiled: December 10, 2015Date of Patent: June 20, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu
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Patent number: 9679833Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.Type: GrantFiled: September 9, 2016Date of Patent: June 13, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
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Patent number: 9653383Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.Type: GrantFiled: June 12, 2015Date of Patent: May 16, 2017Assignee: Alpha & Omega Semiconductor (Cayman), Ltd.Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Ming-Chen Lu, Yan Huo, Aihua Lu
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Patent number: 9646920Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.Type: GrantFiled: June 7, 2014Date of Patent: May 9, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTDInventors: Hongtao Gao, Jun Lu, Ming-Chen Lu, Jianxin Ye, Yan Huo, Hua Pan
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Publication number: 20160379918Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.Type: ApplicationFiled: September 9, 2016Publication date: December 29, 2016Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
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Publication number: 20160315039Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.Type: ApplicationFiled: July 7, 2016Publication date: October 27, 2016Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
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Patent number: 9472491Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.Type: GrantFiled: September 10, 2015Date of Patent: October 18, 2016Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
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Patent number: 9437587Abstract: A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.Type: GrantFiled: January 19, 2014Date of Patent: September 6, 2016Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Xiaotian Zhang, Hamza Yilmaz, Jun Lu, Xiaoguang Zeng, Ming-Chen Lu
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Patent number: 9425181Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.Type: GrantFiled: May 2, 2015Date of Patent: August 23, 2016Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
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Patent number: 9337131Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.Type: GrantFiled: September 29, 2014Date of Patent: May 10, 2016Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Yan Huo, Hamza Yilmaz, Jun Lu, Ming-Chen Lu, Zhi Qiang Niu, Yan Xun Xue, Demei Gong
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Publication number: 20160111343Abstract: A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a semiconductive layer. An insulating layer is disposed at two sides of the fin structure. Then, a dielectric layer conformally covers the floating gate material and insulating layer. Later, a patterned first mask layer, a patterned second mask layer, and a control gate are stacked on the dielectric layer from bottom to top. The control gate crosses at least one fin structure. Next, at least one isotropic etching step is performed to entirely remove the exposed dielectric layer.Type: ApplicationFiled: April 22, 2015Publication date: April 21, 2016Inventors: Ming-Chen Lu, Chia-Ming Wu