METHOD OF FABRICATING FLASH MEMORY
A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a semiconductive layer. An insulating layer is disposed at two sides of the fin structure. Then, a dielectric layer conformally covers the floating gate material and insulating layer. Later, a patterned first mask layer, a patterned second mask layer, and a control gate are stacked on the dielectric layer from bottom to top. The control gate crosses at least one fin structure. Next, at least one isotropic etching step is performed to entirely remove the exposed dielectric layer.
This application claims the benefit of Taiwanese Patent Application No. 103136317, filed on Oct. 21, 2014, the contents of which are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a method of fabricating a flash memory. In particular, the present invention relates to a method of fabricating a flash memory by an isotropic etching process.
2. Description of the Prior Art
Non-volatile semiconductor memories are used in a number of devices, including cellular telephones, digital cameras, personal digital assistants, mobile computing devices and non-mobile computing devices.
As one type of non-volatile memory device, a split gate flash memory device includes a floating gate and a control gate that are separated from each other. The floating gate is electrically isolated from the external environment, and stores information using the characteristic that the current of a memory cell varies according to electron injection to and removal from the floating gate.
When these flash memories are fabricated by conventional processes, however, they may suffer from current leakage between floating gates.
SUMMARY OF THE INVENTIONTo solve the current leakage problem, a new method of fabricating a flash memory is needed.
According to the present invention, a method of fabricating a flash memory includes providing at least a fin structure and an insulating layer disposed at two sides of the fin structure, wherein the fin structure comprises a floating gate material, an oxide layer and a semiconductive layer arranged in a top-down sequence. Part of the floating gate material protrudes from the insulating layer and a height of the insulating layer is greater than a height of the oxide layer. Later, a dielectric layer is formed conformally covering the floating gate material and the insulating layer. Subsequently, a patterned first mask layer, a patterned second mask layer and a control gate are formed to stack in a top-down sequence on part of the dielectric layer, and the remaining part of the dielectric layer is exposed. An extending direction of the patterned first mask layer, an extending direction of the patterned second mask layer and an extending direction of the control gate are perpendicular to an extending direction of the fin structure. After that, at least one first isotropic etching step is performed to remove the exposed dielectric layer until the exposed dielectric layer is removed entirely to expose the floating gate material underneath the exposed dielectric layer. Finally, a floating gate material patterning step is performed, wherein the floating gate material patterning step comprises removing the exposed floating gate material to format least one floating gate.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Next, a patterned mask layer 18 is formed. As shown in
As shown in
The first mask layer and the second mask layer are patterned to form a patterned first mask layer 34 and a patterned second mask layer 36. After that, the metal layer is patterned to form a patterned metal layer 40 and the conductive layer is patterned to form numerous control gates 42 by taking the patterned first mask layer 34 and the patterned second mask layer 36 as a mask to expose the dielectric layer 32 between the control gates 42. At this point, the patterned second mask layer 36, the patterned first mask layer 34, the control gates 42 and the patterned metal layer 40 form numerous strip structures and the extending direction of the strip structures is perpendicular to the extending direction of the fin structures 20.
The control gate 42 may be poly silicon, metal or other conductive materials. The patterned metal layer 40 may be tungsten, copper, or other metals. The patterned metal layer 40 can be replaced by an alloy or metallic compound. In addition, a barrier layer (not shown) can be disposed between the control gate 42 and the patterned metal layer 40. The barrier layer can be titanium nitride or tantalum nitride. The patterned first mask layer 34 may be silicon oxide, silicon nitride, silicon oxynitride, a compound made of silicon nitride and silicon oxide or other suitable materials. The patterned second mask layer 36 may be metal, a metallic compound, alloy or single crystalline silicon or polysilicon. It is noteworthy that the material of the patterned second mask layer 36 must be a material which has a high etching selectivity with respect to silicon oxide and silicon nitride due to a first isotropic etching step and a second isotropic etching step that is performed later.
As shown in
According to a preferred embodiment of the present invention, after the first isotropic etching step is completed and the height H1 of the insulating layer 28 is determined to be smaller than the height H2 of the oxide layer 24, or after the second isotropic etching step is completed and the height H1 of the insulating layer 18 is determined to be smaller than the height H2 of the oxide layer 24, a floating gate material patterning step is performed.
In detail, the floating gate material 22 on the oxide layer 24 not covered by the patterned second mask layer 36 is removed by a dry etch taking the oxide layer 24 as an etching stop layer. Therefore, the oxide layer 24 under the floating gate material layer 22 is exposed. During the floating gate material patterning step, the patterned second mask layer 36 serves as a mask to protect the metal layer 40 and the control gate 42. Since the patterned second mask layer 36 serves as a mask, the patterned second mask layer 36 may be consumed during the floating gate material patterning step. It is possible that the patterned second mask layer 36 is entirely consumed after the floating gate material patterning step, i.e. the floating gate material layer 22 is patterned while the patterned second mask layer 36 is removed. The etchant of the dry etch in the floating gate material patterning step is preferably hydrogen bromide, and the carrier gas is preferably oxygen, but is not limited to those chemical compounds. At this point, the flash memory 100 of the present invention is completed.
In the conventional method of making a flash memory, the floating gate material will be left on the sidewall of the oxide layer 24 which is higher than the insulating layer 28. Therefore, the floating gates 44 will electrically connect to each other through this floating gate material. According to the present invention, a second mask layer 36 is added in the present invention. Furthermore, the dielectric layer 32 is specially removed by an isotropic etching step. In addition, part of the insulating layer 28 between each fin structure 20 is removed by an isotropic etching step. In this way, the problem of the floating gates 44 electrically connecting to each other can be solved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method of fabricating a flash memory, comprising:
- providing at least a fin structure and an insulating layer disposed at two sides of the fin structure, wherein the fin structure comprises a floating gate material, an oxide layer and a semiconductive layer arranged in a top-down sequence, and part of the floating gate material protrudes from the insulating layer and a height of the insulating layer is greater than a height of the oxide layer;
- forming a dielectric layer conformally covering the floating gate material and the insulating layer;
- forming a patterned first mask layer, a patterned second mask layer, and a control gate stacked in a top-down sequence on part of the dielectric layer, and exposing the other part of the dielectric layer, wherein an extending direction of the patterned first mask layer, an extending direction of the patterned second mask layer and an extending direction of the control gate are perpendicular to an extending direction of the fin structure;
- performing at least one first isotropic etching step to remove the exposed dielectric layer until the exposed dielectric layer is removed entirely to expose the floating gate material underneath the exposed dielectric layer; and
- performing a floating gate material patterning step, wherein the floating gate material patterning step comprises removing the exposed floating gate material to form at least one floating gate.
2. The method of fabricating a flash memory of claim 1, further comprising repeating the first isotropic etching step at least once until the exposed dielectric layer is entirely removed.
3. The method of fabricating a flash memory of claim 1, wherein the first isotropic etching step comprises removing part of the insulating layer.
4. The method of fabricating a flash memory of claim 1, further comprising:
- before performing the floating gate material patterning step, checking the height of the insulating layer, and if the height of the insulating layer is smaller than the height of the oxide layer, performing the floating gate material patterning step.
5. The method of fabricating a flash memory of claim 1, further comprising:
- before performing the floating gate material patterning step, checking the height of the insulating layer, and if the height of the insulating layer is greater than the height of the oxide layer, performing a second isotropic etching step to remove part of the insulating layer to make the height of the insulating layer smaller than the height of the oxide layer.
6. The method of fabricating a flash memory of claim 1, wherein when removing the dielectric layer, the patterned first mask layer is removed simultaneously.
7. The method of fabricating a flash memory of claim 1, wherein the patterned first mask layer comprises silicon nitride, silicon oxide or silicon oxynitride.
8. The method of fabricating a flash memory of claim 1, wherein the patterned second mask layer comprises metal, metallic compound, alloy, single crystalline silicon or polysilicon.
9. The method of fabricating a flash memory of claim 1, wherein the dielectric layer comprises oxide-nitride-oxide.
10. The method of fabricating a flash memory of claim 1, wherein the floating gate material comprises single crystalline silicon or polysilicon.
11. The method of fabricating a flash memory of claim 1, wherein the floating gate material patterning step is performed by using the oxide layer as an etching stop layer.
12. The method of fabricating a flash memory of claim 1, wherein the first isotropic etching step utilizes the patterned first mask layer as a mask and utilizes the floating gate material and the insulting layer as etching stop layers.
13. The method of fabricating a flash memory of claim 1, wherein during the floating gate material patterning step, the patterned second mask layer is removed simultaneously.
14. The method of fabricating a flash memory of claim 1, further comprising:
- forming a patterned metal layer between the patterned second mask layer and the control gate, and an extending direction of the patterned metal layer is perpendicular to the extending direction of the fin structure.
Type: Application
Filed: Apr 22, 2015
Publication Date: Apr 21, 2016
Inventors: Ming-Chen Lu (Hsinchu), Chia-Ming Wu (Taipei City)
Application Number: 14/693,857