Abstract: The present disclosure provides an electronic device including a substrate, a semiconductor disposed on the substrate, and a conductive layer disposed on the semiconductor. The conductive layer has a first electrode and a second electrode, in which the first electrode is electrically connected to the semiconductor, and the second electrode surrounds the first electrode in a top view direction of the electronic device.

Abstract: The present application provides a method for determining a stability of a welding equipment. The method includes acquiring initial welding images of the welding equipment; obtaining at least one welding spot position of each of at least one welded workpiece in each initial welding image by processing the initial welding images; determining a welding center position of each welded workpiece based on the at least one welding spot position of each welded workpiece, and obtaining welding center positions of all welded workpieces comprised in the initial welding images; and determining a stability of welding equipment based on the welding center positions of all welded workpieces. The method determines whether the welding equipment is stable by analyzing the welding images, thereby improving an accuracy of a detection of a stability of the welding equipment.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A power module including at least one power device, an insulation thermally conductive layer, and a heat dissipation device is provided. The insulation thermally conductive layer has a patterned circuit layer. The power device is disposed on the patterned circuit layer and is electrically connected to the patterned circuit layer. The heat dissipation device includes a heat dissipation plate and a heat dissipation base. The heat dissipation plate has a first surface and a second surface opposite to each other, and the insulation thermally conductive layer is disposed on the first surface. The heat dissipation base is partially bonded to the heat dissipation plate, and a chamber is formed between the heat dissipation plate and the heat dissipation bases. The heat dissipation base has a plurality of first heat dissipation bumps located in the chamber.

Abstract: The disclosure provides an electronic assembly, a method for manufacturing electronic assembly, and a composite thermally conductive sheet. The electronic assembly includes a circuit board, a heat source, an anti-overflow element, a thermally conductive block and a thermally conductive sheet. The heat source is disposed on and electrically connected to the circuit board. The anti-overflow element is disposed on a side of the heat source located farthest away from the circuit board and has an opening. The thermally conductive block is disposed on a side of the anti-overflow element located farthest away from the heat source. The thermally conductive sheet is made of a phase change material. The thermally conductive sheet is located in the opening of the anti-overflow element to be surrounded by the anti-overflow element. Opposite sides of the thermally conductive sheet are in thermal contact with the heat source and the thermally conductive block, respectively.

Abstract: A display panel including an array substrate, a light-emitting diode chip, a photosensitive material layer and a photosensitive material layer. The array substrate includes a first electrode pad and a second electrode pad adjacent to the first electrode pad. The light-emitting diode chip includes a first electrode and a second electrode at opposite sides of the light-emitting diode chip, and the first electrode is connected with the first electrode pad. The photosensitive material layer is over the array substrate and surrounds the light-emitting diode chip, in which the photosensitive material layer includes an opening exposing the second electrode pad, a sidewall of the opening has a first portion and a second portion, a slope of the first portion is greater than a slope of the second portion. The transparent conductive layer is over the photosensitive material layer and electrically connects the second electrode pad and the second electrode.

Abstract: Disclosed herein are device and method for performing a total internal reflection scattering (TIRS) measurement to a sample slide. The device comprises a first reflective plate having a first opening; a second reflective plate having second and third openings and disposed on top of the first reflective plate thereby forming a slot therebetween for accommodating the sample slide, wherein the first opening of the first reflective plate is disposed directly underneath the second opening of the second reflective plate; a white light source disposed in the space formed by the third opening of the second reflective plate and configured to emit a white light into the slot; and a first blackout layer disposed on top of the third opening thereby covering the white light source and keeping the emitted white light from leaking. When the sample slide is inserted into the slot, the white light source illuminates the sample slide so as to achieve the TIRS measurement to the sample slide.

Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.

Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: A method for preparing quartz glass with low content of hydroxyl and high purity, includes providing silica powders including hydroxyl groups. The silica powders are dehydroxylated, which includes drying the silica powders at a first temperature, heating the silica powders up to a second temperature and introducing a first oxidizing gas including halogen gas, thereby obtaining first dehydroxylated powders, and heating the first dehydroxylated powders up to a third temperature and introducing a second oxidizing gas including oxygen or ozone, thereby obtaining second dehydroxylated powders. The second dehydroxylated powders are heated up to a fourth temperature to obtain a vitrified body. The vitrified body is cooled to obtain the quartz glass with low content of hydroxyl and high purity. The quartz glass prepared by the above method has low content of hydroxyl and high purity. A quartz glass with low content of hydroxyl and high purity is also provided.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A user equipment (UE) includes one or more non-transitory computer-readable media containing computer-executable instructions embodied therein, and at least one processor coupled to the one or more non-transitory computer-readable media. The at least one processor configured to execute the computer-executable instructions to receive downlink control information (DCI) on a downlink (DL) channel of a non-terrestrial network (NTN), the DL channel reception ending in a first slot, and transmit an uplink (UL) transmission on a UL channel of the NTN in a second slot. The second slot is separate from the first slot by a timing offset, where a duration of the timing offset is dependent on a type of the UL transmission and a numerology of the UL transmission.

Abstract: A control method in use of a flyback power converter is disclosed to provide an operation power source supplying power to a power controller controlling a main power switch. The flyback power converter has a transformer with a primary winding and an auxiliary winding. The main power switch and the primary winding are connected in series. A chopper switch and a buffer inductor are connected in series between the auxiliary winding and the power controller. The power controller turns ON the main power switch for an ON time to energize the transformer, and turns ON the chopper switch for at least a time period during the ON time, so that during the time period the buffer inductor conducts an induced current flowing from the auxiliary winding and through the chopper switch, to build up the operation power source.