Abstract: The present invention discloses a protein transformation method based on an amino acid knowledge graph and active learning, including: building an amino acid knowledge graph based on biochemical attributes of amino acids; enhancing protein data in combination with the amino acid knowledge graph to obtain enhanced protein data, and performing representation learning to obtain first enhanced protein representations; performing representation learning on the protein data or the protein data and the amino acid knowledge graph by using a pre-trained protein model to obtain second enhanced protein representations; synthesizing the first enhanced protein representations and the second enhanced protein representations to obtain enhanced protein representations; taking the enhanced protein representations as samples, and through active learning, screening out representative samples from the samples, manually annotating protein properties, and training a protein property prediction model by using the manually annotated

Abstract: A heat sink, a separator, and a lighting device applying the same are provided. The heat sink comprises: a housing, formed around an axis, wherein the housing has a first open end and a second open end along the axis, and a holding cavity connecting the two open ends. The housing comprises a first portion and a second portion, both formed around the axis, wherein the first portion comprises several device mounting portions distributed around the axis. The second portion comprises an outer fin set disposed around the axis in an outer peripheral region, and an inner fin set disposed around the axis in an inner peripheral region; the first portion is closer to the first open end than the second portion is to the first open end, and the outer fin set extends toward the second open end; each fin extends toward the axis.

Abstract: An electronic device including a protective substrate is provided. The protective substrate includes a substrate and an anti-reflection layer. The anti-reflection layer is disposed on the substrate. The anti-reflection layer includes a first sublayer to an nth sublayer sequentially arranged on the substrate, where n is greater than 1, and a product range of a thickness and a refractive index of the nth sublayer ranges from 100 nm to 170 nm.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A docker image is received. The docker image is for a container. The container contains files that allow for virtualization of applications that run within the container. The docker image is parsed to identify layer files in the docker image. Installed software components (e.g., installed files) and/or hardware components in the layer files are identified. Software application index calls are made to generate information that identifies relationships between the installed software components and/or hardware components. The relationships between the installed software components and/or hardware components are then displayed to a user.

Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

Abstract: The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. The accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.

Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.

Abstract: A method for determining phase locking of critical arc light includes: step 1: monitoring and collecting light radiation intensity of an arc inside a switch cabinet in real time, and converting the collected light radiation intensity into an electrical signal; step 2: extracting a power-frequency fundamental wave of the electrical signal, comparing an amplitude of the power-frequency fundamental wave of the electrical signal with a first threshold, and generating a pre-warning signal based on a comparison result of the first threshold; step 3: comparing the amplitude of the power-frequency fundamental wave of the electrical signal with a second threshold voltage, and generating a control signal based on a comparison result of the second threshold voltage and a protection time threshold; and step 4: protecting the switch cabinet under the critical arc light environment based on the pre-warning signal and the control signal.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A riding mowing device includes a seat used for a user to sit on and including a seat cushion and a backrest; a frame for supporting the seat; a cutting assembly including a cutting deck and a mowing element for mowing grass, where the mowing element is at least partially accommodated in the cutting deck, and the cutting assembly is mounted to the frame; a traveling assembly for driving the riding mowing device to travel; a control circuit board for controlling at least the cutting assembly and the traveling assembly; and a power supply assembly for supplying power to at least the cutting assembly and the traveling assembly. At least part of the control circuit board is disposed between the seat and the power supply assembly.

Abstract: A semiconductor manufacturing method is provided. The semiconductor manufacturing method includes the following steps. A first semiconductor element with a bonding film and a first stressing film is formed. The first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. The first stressing film makes the first bonding film to have a first convex surface. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on one side of the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.

Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.

Abstract: Systems and methods for manhole localization along deployed fiber optic cables that employs cross-correlation methodologies and ambient road traffic operating proximate to the manholes including fiber optic telecommunications cables to detect the manhole locations using distributed fiber optic sensing (DFOS). Advantageously the manhole locations are determined without employing labor intensive field surveys.

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask.