Abstract: A communication system, method, and components are described. Specifically, a communication method is disclosed which enables a media device and control device to be dynamically paired to one another and a control link call to be established between the media device and the control device. The control link call can be utilized to permit the media device to be controlled by the control device while the media device exchanges media with a communication device operated by another user.

Abstract: A communication system, method, and components are described. Specifically, a communication method is disclosed which enables a media device and control device to be dynamically paired to one another and a control link call to be established between the media device and the control device. The control link call can be utilized to permit the media device to be controlled by the control device while the media device exchanges media with a communication device operated by another user.

Abstract: A communication system, method, and components are described. Specifically, a communication system having the ability to enable a media server to provide audio substitution during a dynamic device pairing scenario is disclosed. The media server may be included in the call topology, for instance, by way of a dynamic device pairing server or application that facilitates the dynamic pairing of a media device and a control device for a communication session.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Abstract: A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Abstract: An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Abstract: A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads.

Abstract: A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield/lifetime domain, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: A capacitive keyboard device with a keystroke triggering threshold adaptively adjustable capability is proposed, which is designed for integration to an electronic unit, such as PDA (Personal Digital Assistant) computers, mobile phone unit, and calculator, for use as a data input device for the electronic unit. The proposed capacitive keyboard device is characterized by the operation of a triggering threshold adaptive adjustment function that can adaptively adjust the keystroke triggering threshold of the capacitive keyboard device in response to the user's habitual key-pressing action during each use, which also takes account of all internal factors (such as decay of the capacitor structure) and external factors (such as physical characteristics of the user's fingers). This feature allows the capacitive keyboard device to be reliable in operation for long period of use.

Abstract: A capacitive keyboard device with a keystroke triggering threshold adaptively adjustable capability is proposed, which is designed for integration to an electronic unit, such as PDA (Personal Digital Assistant) computers, mobile phone unit, and calculator, for use as a data input device for the electronic unit. The proposed capacitive keyboard device is characterized by the operation of a triggering threshold adaptive adjustment function that can adaptively adjust the keystroke triggering threshold of the capacitive keyboard device in response to the user's habitual key-pressing action during each use, which also takes account of all internal factors (such as decay of the capacitor structure) and external factors (such as physical characteristics of the user's fingers). This feature allows the capacitive keyboard device to be reliable in operation for long period of use.

Abstract: A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum pad layer which includes a plurality of aluminum pads and a plurality of dummy patterns, wherein the dummy patterns are distributed in the spaces between the aluminum pads. Besides, routings can be further disposed in the aluminum pad layer and the dummy patterns are distributed in the spaces between the aluminum pads, between the aluminum pads and the routings, or between the routings.

Abstract: An audio-video (AV) signal transceiving processing device which includes a AV decoder, a bridge, and a bus interface, wherein the bus interface is a PCMCIA, CardBus, or Express Card bus interface. The AV decoder is used to receive an analog video signals and a corresponding analog audio signal, and output a first digital video signal and a corresponding first digital audio signal. The bridge is used to receive the first digital video signal and the first digital audio signal, and output a second digital video signal and a second digital audio signal, which are compliant to a bus interface standard, to a computer through a bus interface that is compliant to the bus interface standard.

Abstract: A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads.

Abstract: A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum pad layer which includes a plurality of aluminum pads and a plurality of dummy patterns, wherein the dummy patterns are distributed in the spaces between the aluminum pads. Besides, routings can be further disposed in the aluminum pad layer and the dummy patterns are distributed in the spaces between the aluminum pads, between the aluminum pads and the routings, or between the routings.

Abstract: A video signal processing apparatus and a computer system integrated with the video signal processing apparatus are disclosed. The video signal processing apparatus has a tuner, a video processor, a non-interlaced signal processing unit, a microprocessor, and a computer signal converter. In the video signal processing apparatus, the display can be instantly turned on and the video signal can be recorded in the storage media of a computer, and the video signal recorded in the storage media can be displayed on the display. While watching the video signal on the display, a user can execute applications in the computer simultaneously. The video signal processing apparatus further provides picture-in-picture feature by adding another set of tuner and video processor. The video signal processing apparatus can be integrated with a display or a computer, and can also be used as an external-enclosure video signal processing apparatus.

Abstract: Methods to identify genes, the expression of which are altered in response to pathogen infection, are provided, as well as the genes identified thereby and their corresponding promoters.