Abstract: The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved.

Abstract: The present disclosure discloses an array substrate, belongs to the technical field of display technology, and solves the technical problem of low aperture ratio of prior liquid crystal display device. The array substrate comprises a plurality of sub pixel units arranged in an array and a plurality of signal lines, wherein one signal line of two adjacent signal lines is arranged in a first side of corresponding sub pixel units, and the other signal line is arranged in a second side of corresponding sub pixel units, said first side and said second side being one of opposite sides of the sub pixel units respectively. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices.

Abstract: The present invention provides a display panel and a wiring structure thereof. The wiring structure comprises a plurality of metal wires extending across a first wiring region, a second wiring region, and a third wiring region. The first wiring region adjoins the second wiring region. The second wiring region adjoins the third wiring region. A line width of an nth metal wire in the second wiring region is a, and a distance between the nth metal wire and an n+1th metal wire is b, where n?1. When n is taken as different values, a/(a+b) is a constant value. According to the above method, the coverage ratio in the seal coating region by the metal wires is not changed to avoid the problem of uneven curing of the sealant. The performance stability of the display panel is thus not impacted.

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract: An array substrate and a display panel are disclosed. The array substrate includes at least one data line, at least one scanning line, and a pixel cell defined by the data line and the scanning line. The pixel cell includes an ITO thin film and at least one metallic layer below the ITO thin film. The ITO thin film electrically connects to the metallic layer via a through hole. The ITO thin film includes a slit arranged between the ITO thin film and the through hole, and the slit is arranged to avoid the disclination lines so as to improve the display performance.

Abstract: The present disclosure proposes a method for curing a sealant in manufacturing of a liquid crystal panel. The liquid crystal panel includes an array substrate, a color filter substrate and a liquid crystal layer between the array substrate and the color filter substrate, a first film layer capable of blocking light is arranged on the side of the color filter substrate facing the liquid crystal layer, and a sealant is arranged between the array substrate and the color filter substrate outside the liquid crystal layer, and the method includes: step 1, removing a portion of the first film layer corresponding to the sealant; and step 2, applying UV from one side of the color filter substrate of the liquid crystal panel to irradiate the sealant, thus curing the sealant. The present disclosure also proposes a liquid crystal panel.

Abstract: The present invention discloses a liquid crystal display (LCD) panel which includes a thin film transistor array substrate, a color filter substrate, a liquid crystal layer and a frame. The color filter substrate includes a transparent substrate, a black matrix layer and a coloring layer. The frame is disposed at an outer side edge of the liquid crystal layer. The present invention further discloses a method for manufacturing the LCD panel. The present invention can block an UV light by the black matrix layer and the coloring layer, and an UV mask can be omitted.

Abstract: The present invention provides a liquid crystal display panel, which comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer; the first insulating layer being disposed on the first conductive layer and comprising at least two first via-holes corresponding respectively to at least two first subsidiary conductive regions so that at least two first subsidiary conductive regions being partially exposed through first via-holes; the second conductive layer being disposed on the first insulating layer; the second insulating layer being disposed on the second conductive layer; the second insulating layer being disposed on the second conductive layer and comprising at least two second via-holes corresponding respectively to at least two second subsidiary; a third conductive layer being connected with first subsidiary conductive regions and a second conductive layer.

Abstract: The present disclosure provides a detection circuit for a display panel, comprising: a shorting bar, with connection lines for introducing a test signal or a control signal arranged thereon; a transistor array, the gates of which are connected to the connection lines for introducing the control signal, wherein the connection lines for introducing the test signal are connected with the data lines or the scanning lines of the display panel via the sources and the drains of transistors, under the control signal, and a component, arranged between the gates of the transistor array and the shorting bar, for further reducing or increasing a voltage or current of the gates so that the transistor array can be cut off reliably when the control signal is a signal enabling the transistor array to be cut off. The detection circuit can further reduce the channel length of the thus being advantageous for the design of the narrow frame.

Abstract: An array substrate and a display panel are disclosed. The array substrate includes at least one data line, at least one scanning line, and a pixel cell defined by the data line and the scanning line. The pixel cell includes an ITO thin film and at least one metallic layer below the ITO thin film. The ITO thin film electrically connects to the metallic layer via a through hole. The ITO thin film includes a slit arranged between the ITO thin film and the through hole, and the slit is arranged to avoid the disclination lines so as to improve the display performance.

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract: A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets.

Abstract: A display panel and a liquid crystal device are disclosed. The display panel includes a first substrate, a second substrate opposite to the first substrate, a sealant. The first substrate is arranged with a first alignment film. The second substrate is arranged with a second alignment film. The sealant surrounds the first substrate and the second substrate. A first wall is arranged on the first substrate, and the first wall is between an edge of the first alignment film and the sealant. A second wall is arranged on the second substrate, and the second wall is between an edge of the second alignment film and the plastic film. In this way, the distance between an active area and edges of the display panel is reduced so that the narrow bezel design may be implemented.

Abstract: The present invention discloses a thin film transistor (TFT) array substrate, which includes a plurality of scan lines, data lines, and common electrode lines disposed on a substrate. The scan lines and the data lines cross with each other to define a plurality of pixel regions that have a plurality of TFTs disposed in the crossing regions therebetween. A plurality of pixel electrodes are disposed in the pixel regions. The TFT array substrate further includes a patterned shielding layer which is insulatively disposed below the data lines. The patterned shielding layer of the present invention can shield the back light directly, and the area of the black matrix on the color filter substrate can be reduced so as to increase the aperture ratio.

Abstract: The present invention provides a display panel and a wiring structure thereof. The wiring structure comprises a plurality of metal wires extending across a first wiring region, a second wiring region, and a third wiring region. The first wiring region adjoins the second wiring region. The second wiring region adjoins the third wiring region. A line width of an nth metal wire in the second wiring region is a, and a distance between the nth metal wire and an n+1th metal wire is b, where n?1. When n is taken as different values, a/(a+b) is a constant value. According to the above method, the coverage ratio in the seal coating region by the metal wires is not changed to avoid the problem of uneven curing of the sealant. The performance stability of the display panel is thus not impacted.

Abstract: A fan module includes a casing, a fan, and two vibration absorption assemblies. The casing has an accommodating space. The fan is located in the accommodating space and keeps a distance from the casing. Each of the two vibration absorption assemblies includes two first vibration absorption components and a second vibration absorption component. The two first vibration absorption components are respectively in contact with the fan and separated from the casing, respectively. The second vibration absorption component is connected with two first vibration absorption components and the casing, respectively. The first vibration absorption components and the second vibration absorption components are adapted for absorbing the vibration waves having different frequency ranges.

Abstract: A memory expansion assembly includes a first plate having first electrical slots and a first electrically connecting portion, a second plate pivotally connected to the first plate and having second electrical slots and a second electrically connecting portion, a first engaging assembly, and a second engaging assembly. The first electrical slots are electrically connected to the first electrically connecting portion. The second electrical slots are electrically connected to the second electrically connecting portion. The second plate is adapted to pivot relative to the first plate to have a folded position when the two are close to each other and an unfolded position when the two are away from each other. The first engaging assembly is disposed on a side of the first plate. The second engaging assembly is disposed on a side of the second plate. The first engaging assembly is removably engaged with the second engaging assembly.

Abstract: A memory combination is applied in a computer system. The computer system includes a motherboard. The motherboard includes a first riser slot and a second riser slot disposed side by side. The memory combination includes a first riser board and a second riser board. The first riser board is plugged into the first riser slot and includes a plurality of first memory sockets. The second riser board is plugged into the second riser slot and includes a plurality of second memory sockets. The first memory sockets face the second riser board, and the second memory sockets face the first riser board. The first memory sockets are unaligned with the second memory sockets.

Abstract: A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets.

Abstract: A fan structure includes a casing, a fan, and two elastic members. The casing has an accommodation space. The fan is located in the accommodation space. The fan has a first side and a second side opposite to each other. One of the two elastic members is sandwiched between the casing and the first side of the fan. The other one of the two elastic members is sandwiched between the casing and the second side of the fan. The two elastic members normally keep the fan away from the casing, so as to make the fan contact the casing through the two elastic members, thereby achieving a damping effect.