Abstract: The present invention proposes to a flat display panel and a method for forming the same. The flat display panel includes a plurality of rows of scan lines, a plurality of columns of data lines and a plurality of blocking lines which are parallel and overlapped to the data lines. The plurality of blocking lines are placed at one side of pixel electrodes one on one and made of the same metallic layer with the plurality of scan lines. Each blocking line made of the same metallic layer with the scan line is wider than a corresponding data line, so that light not blocked by the data line is blocked by the wider blocking line.

Abstract: The present invention provides a liquid crystal display panel, which comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer; the first insulating layer being disposed on the first conductive layer and comprising at least two first via-holes corresponding respectively to at least two first subsidiary conductive regions so that at least two first subsidiary conductive regions being partially exposed through first via-holes; the second conductive layer being disposed on the first insulating layer; the second insulating layer being disposed on the second conductive layer; the second insulating layer being disposed on the second conductive layer and comprising at least two second via-holes corresponding respectively to at least two second subsidiary; a third conductive layer being connected with first subsidiary conductive regions and a second conductive layer.

Abstract: A display panel and a liquid crystal device are disclosed. The display panel includes a first substrate, a second substrate opposite to the first substrate, a sealant. The first substrate is arranged with a first alignment film. The second substrate is arranged with a second alignment film. The sealant surrounds the first substrate and the second substrate. A first wall is arranged on the first substrate, and the first wall is between an edge of the first alignment film and the sealant. A second wall is arranged on the second substrate, and the second wall is between an edge of the second alignment film and the plastic film. In this way, the distance between an active area and edges of the display panel is reduced so that the narrow bezel design may be implemented.

Abstract: An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.

Abstract: The present invention relates to a chip-on-film panel structure, which has a panel body and fan-out leads, first metal sheets, array leads and second metal leads thereon. The array leads are disposed at two sides of the fan-out leads, the second metal sheets are disposed at two sides of the first metal sheets, and the length of each of the second metal sheet is less than the length of each of the first metal sheet to form a lead-out area that the array leads are led out from the second metal sheets via the lead-out area. The chip-on-film panel structure having an arranged fan-out area for array leads can settle the problem of being difficult to narrow the frame of the panel because the array leads occupy available room for fan-out leads and force the fan-out area to expand longitudinally.

Abstract: A pixel structure having the following structure is provided. A light-shielding layer with a flat layer covering thereon is disposed on a substrate. A channel layer, a data line and a first pad are disposed on the flat layer. A source and a drain partially cover two sides of the channel layer. A gate dielectric layer with a gate, a scan line and a second pad disposed thereon covering the channel layer, the source and the data line exposes the drain and the first pad. A protection layer covering the gate and the scan line exposes the drain, the first and second pads. A patterned transparent conductive layer includes a pixel electrode disposed on the protection layer, a first retain portion disposed on the first pad and a second retain portion disposed on the second pad.

Abstract: The present invention discloses a liquid crystal display device and liquid crystal display module thereof. The liquid crystal display module includes a color filter substrate, a thin film transistor substrate and seal. The thin film transistor substrate and the color film substrate are disposed oppositely, and the seal is disposed between the thin film transistor substrate and the color film substrate. The color filter substrate comprises a first glass substrate and black matrix. The seal comprises a first end part contacting the color filter substrate. No black matrix is disposed between the first end part and the color filter substrate, and the first end part is disposed as a shade structure. The liquid crystal display module and liquid crystal display device of the present invention provide the advantages of convenience for seal curing, facilitating narrow border design, and avoiding aggravating drive signal delay.

Abstract: A liquid crystal display (LCD) module is disclosed, which comprises a thin film transistor (TFT) substrate and a color filter (CF) substrate disposed opposite to each other, and a liquid crystal layer sandwiched between the TFT substrate and the CF substrate. The TFT substrate comprises a plurality of transmission test units and a plurality of wires. The CF substrate comprises a plurality of curing test units insulated from each other, and each of the curing test units is electrically connected to one of the wires via one of the transmission test units. An LCD device and a manufacturing method of an LCD module are further disclosed. The LCD device, the LCD module and the manufacturing method thereof according to the present disclosure can avoid occurrence of arcing in the TFT substrate during the CVD process, thereby improving the product yield and reducing the manufacturing cost.

Abstract: A server cabinet includes a rack, at least one assembling frame, a radiator and at least one fan. The rack has a first frame and a second frame opposite to each other. The assembling frame and the radiator are mounted on the first frame in sequence. The radiator transfers a coolant to flow inside a plurality of heatsink fins thereof in a circulating manner. The fan is mounted in the assembling frame, and the fan guides an airflow to flow into the first frame from the radiator, and blows the airflow in the rack to the second frame, thus lowering the temperature inside the rack.

Abstract: The present invention proposes to a flat display panel and a method for forming the same. The flat display panel includes a plurality of rows of scan lines, a plurality of columns of data lines and a plurality of blocking lines which are parallel and overlapped to the data lines. The plurality of blocking lines are placed at one side of pixel electrodes one on one and made of the same metallic layer with the plurality of scan lines. Each blocking line made of the same metallic layer with the scan line is wider than a corresponding data line, so that light not blocked by the data line is blocked by the wider blocking line.

Abstract: A liquid crystal display (LCD) module is disclosed, which comprises a thin film transistor (TFT) substrate and a color filter (CF) substrate disposed opposite to each other, and a liquid crystal layer sandwiched between the TFT substrate and the CF substrate. The TFT substrate comprises a plurality of transmission test units and a plurality of wires. The CF substrate comprises a plurality of curing test units insulated from each other, and each of the curing test units is electrically connected to one of the wires via one of the transmission test units. An LCD device and a manufacturing method of an LCD module are further disclosed. The LCD device, the LCD module and the manufacturing method thereof according to the present disclosure can avoid occurrence of arcing in the TFT substrate during the CVD process, thereby improving the product yield and reducing the manufacturing cost.

Abstract: A liquid crystal display (LCD) module is disclosed, which comprises: a thin film transistor (TFT) substrate and a color filter (CF) substrate disposed opposite to each other, and a liquid crystal layer sandwiched between the TFT substrate and the CF substrate. The TFT substrate comprises a plurality of wires including at least a first group of wires and a second group of wires, and the second group of wires comprises at least two wires. The CF substrate comprises first curing test units and second curing test units insulated from each other. The first curing test units are electrically connected with the first group of wires, and the second curing test units are electrically connected with all the wires of the second group of wires. A manufacturing method of an LCD module is further disclosed.

Abstract: A liquid crystal display panel and its manufacturing method are proposed. The liquid crystal display includes pixels, scan lines, and data lines. The scan lines are formed by a first metallic layer. Each pixel includes multiple subpixels. Each subpixel includes a pixel electrode, a thin-film transistor, and a common electrode line. The common electrode line includes a main branch, a first shielding metallic area, and a second shielding metallic area. The first and second shielding metallic areas are parallel to the scan lines and are connected to the main branch. The data lines and the common electrode lines are formed by the second metallic layer. The scan line and the common electrode line are formed after the first and second metallic layers undergo different etching processes, causing the distance between the scan line and the common electrode line to be shortened and the width of the common electrode line serving as a shielding metallic area partially to be properly decreased.

Abstract: The present invention relates to a chip-on-film panel structure, which has a panel body and fan-out leads, first metal sheets, array leads and second metal leads thereon. The array leads are disposed at two sides of the fan-out leads, the second metal sheets are disposed at two sides of the first metal sheets, and the length of each of the second metal sheet is less than the length of each of the first metal sheet to form a lead-out area that the array leads are led out from the second metal sheets via the lead-out area. The chip-on-film panel structure having an arranged fan-out area for array leads can settle the problem of being difficult to narrow the frame of the panel because the array leads occupy available room for fan-out leads and force the fan-out area to expand longitudinally.

Abstract: An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.

Abstract: An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.

Abstract: A server cabinet structure includes a rack, at least one tray and at least one fixing component. The rack has two opposite frame bars and at least two guide rails correspondingly disposed on the frame bars. The tray is disposed on the two guide rails, and is capable of sliding into the rack. The guide rails are accommodated in recessed portions of the tray exactly. The tray presses against the frame bars through a stop plate. One combining hole of the stop plate is corresponding to an assembly hole of the frame bar. The fixing component passes through the combining hole and the assembly hole, and is inserted into the frame bar, so as to limit and keep the tray inside the rack.

Abstract: A server cabinet includes a rack, at least one assembling frame, a radiator and at least one fan. The rack has a first frame and a second frame opposite to each other. The assembling frame and the radiator are mounted on the first frame in sequence. The radiator transfers a coolant to flow inside a plurality of heatsink fins thereof in a circulating manner. The fan is mounted in the assembling frame, and the fan guides an airflow to flow into the first frame from the radiator, and blows the airflow in the rack to the second frame, thus lowering the temperature inside the rack.

Abstract: A server cabinet structure with a vibration isolation function includes a rack, a accommodated frame, and an isolator. The accommodated frame is installed on the rack, and is disposed in an accommodation room defined the rack. The isolator is installed in the accommodated frame, and is partially exposed out of the rack. The isolator does not increase volume of the server cabinet additionally, and is suitable for being applied to application environment which has narrow spaces.

Abstract: A pixel structure having the following structure is provided. A light-shielding layer with a flat layer covering thereon is disposed on a substrate. A channel layer, a data line and a first pad are disposed on the flat layer. A source and a drain partially cover two sides of the channel layer. A gate dielectric layer with a gate, a scan line and a second pad disposed thereon covering the channel layer, the source and the data line exposes the drain and the first pad. A protection layer covering the gate and the scan line exposes the drain, the first and second pads. A patterned transparent conductive layer includes a pixel electrode disposed on the protection layer, a first retain portion disposed on the first pad and a second retain portion disposed on the second pad.