Patents by Inventor Ming-Kai Liu
Ming-Kai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9543263Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.Type: GrantFiled: November 12, 2013Date of Patent: January 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Wen Shih, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Shih-Wei Liang, Yen-Ping Wang
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Patent number: 9484308Abstract: A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation.Type: GrantFiled: June 25, 2014Date of Patent: November 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Kai Liu, Chao-Wen Shih, Yung-Ping Chiang
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Patent number: 9472523Abstract: A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace.Type: GrantFiled: January 14, 2014Date of Patent: October 18, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Miao, Shih-Wei Liang, Yen-Ping Wang, Kai-Chiang Wu, Ming-Kai Liu
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Patent number: 9460989Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: GrantFiled: February 18, 2014Date of Patent: October 4, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20160254169Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
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Patent number: 9412661Abstract: A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate.Type: GrantFiled: November 21, 2012Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Lu, Ming-Kai Liu, Kai-Chiang Wu, Ching-Feng Yang
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Patent number: 9391012Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.Type: GrantFiled: March 4, 2015Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
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Patent number: 9373599Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: GrantFiled: November 12, 2014Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Kai Liu, Kai-Chiang Wu, Hsien-Wei Chen, Shih-Wei Liang
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Patent number: 9355924Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.Type: GrantFiled: December 21, 2012Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
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Patent number: 9331023Abstract: Some embodiments of the present disclosure provide a semiconductive device, including a semiconductive substrate. A conductive pad is on the semiconductive substrate. A passivation layer covers the conductive pad and overlies the semiconductive substrate. A first protective layer overlies the passivation layer. The first protective layer includes an opening exposing a portion of the passivation layer, and the opening includes at least two lines in contact with each other. A post passivation interconnect (PPI) layer overlies the first protective layer. A conductor forms on the PPI layer.Type: GrantFiled: November 28, 2014Date of Patent: May 3, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Kai Liu, Yu-Peng Tsai, Kai-Chiang Wu, Wei-Hung Lin, Hao-Yi Tsai, Mirng-Ji Lii
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Publication number: 20150380357Abstract: A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: MING-KAI LIU, CHAO-WEN SHIH, YUNG-PING CHIANG
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Publication number: 20150200173Abstract: A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHIA-CHUN MIAO, SHIH-WEI LIANG, YEN-PING WANG, KAI-CHIANG WU, MING-KAI LIU
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Publication number: 20150179561Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.Type: ApplicationFiled: March 4, 2015Publication date: June 25, 2015Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
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Patent number: 9064873Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.Type: GrantFiled: July 30, 2013Date of Patent: June 23, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang
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Publication number: 20150130020Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
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Publication number: 20150125997Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.Type: ApplicationFiled: November 7, 2013Publication date: May 7, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
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Publication number: 20150118797Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu
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Publication number: 20150108635Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: SHIH-WEI LIANG, HSIN-YU PAN, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, CHIA-CHUN MIAO
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Patent number: 8994176Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.Type: GrantFiled: December 13, 2012Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
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Publication number: 20150069606Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: ApplicationFiled: November 12, 2014Publication date: March 12, 2015Inventors: Ming-Kai Liu, Kai-Chiang Wu, Hsien-Wei Chen, Shih-Wei Liang