Patents by Inventor Ming-Kai Liu
Ming-Kai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8994176Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.Type: GrantFiled: December 13, 2012Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
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Publication number: 20150069606Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: ApplicationFiled: November 12, 2014Publication date: March 12, 2015Inventors: Ming-Kai Liu, Kai-Chiang Wu, Hsien-Wei Chen, Shih-Wei Liang
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Publication number: 20150061116Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHUN-LIN LU, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG, SHIH-WEI LIANG, CHING-FENG YANG, CHIA-CHUN MIAO, HAO-YI TSAI
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Publication number: 20150035161Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHIA-CHUN MIAO, SHIH-WEI LIANG, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG
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Patent number: 8941202Abstract: A method for forming an image sensor device is provided. First, a lens is provided and a first sacrificial element is formed thereon. An electromagnetic interference layer is formed on the lens and the first sacrificial element, and the first sacrificial element and electromagnetic interference layer thereon are removed to form an electromagnetic interference pattern having an opening exposing a selected portion of the lens. A second sacrificial element is formed in the opening to cover a center region of the selected portion of the lens. A peripheral region of the selected portion of the lens remains exposed. A light-shielding layer is formed on the electromagnetic interference pattern, second sacrificial element, and peripheral region of the selected portion of the lens. The second sacrificial element and light-shielding pattern are removed to expose the center region of the selected portion of the lens as a light transmitting region.Type: GrantFiled: September 5, 2013Date of Patent: January 27, 2015Assignees: OmniVision Technologies, Inc., VisEra Technologies Company LimitedInventors: Ming-Kai Liu, Tzu-Wei Huang, Jui-Hung Chang, Chia-Hui Huang, Teng-Sheng Chen
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Publication number: 20150008575Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.Type: ApplicationFiled: July 3, 2013Publication date: January 8, 2015Inventors: MING-KAI LIU, CHUN-LIN LU, KAI-CHIANG WU, SHIH-WEI LIANG, CHING-FENG YANG, YEN-PING WANG, CHIA-CHUN MIAO
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Publication number: 20150001704Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.Type: ApplicationFiled: June 26, 2013Publication date: January 1, 2015Inventors: Chun-Lin LU, Kai-Chiang WU, Ming-Kai LIU, Yen-Ping WANG, Shih-Wei LIANG, Ching-Feng YANG, Chia-Chun MIAO, Hung-Jen LIN
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Patent number: 8901730Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: GrantFiled: May 3, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Kai Liu, Shih-Wei Liang, Hsien-Wei Chen, Kai-Chiang Wu
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Publication number: 20140252657Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Kai Liu, Chia-Chun Miao, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chun-Lin Lu
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Publication number: 20140167263Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.Type: ApplicationFiled: December 13, 2012Publication date: June 19, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
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Publication number: 20140162405Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: ApplicationFiled: February 18, 2014Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20140138816Abstract: A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Lin Lu, Ming-Kai Liu, Kai-Chiang Wu, Ching-Feng Yang
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Publication number: 20140117555Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.Type: ApplicationFiled: December 21, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
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Patent number: 8664768Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: GrantFiled: May 3, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20140001590Abstract: A method for forming an image sensor device is provided. First, a lens is provided and a first sacrificial element is formed thereon. An electromagnetic interference layer is formed on the lens and the first sacrificial element, and the first sacrificial element and electromagnetic interference layer thereon are removed to form an electromagnetic interference pattern having an opening exposing a selected portion of the lens. A second sacrificial element is formed in the opening to cover a center region of the selected portion of the lens. A peripheral region of the selected portion of the lens remains exposed. A light-shielding layer is formed on the electromagnetic interference pattern, second sacrificial element, and peripheral region of the selected portion of the lens. The second sacrificial element and light-shielding pattern are removed to expose the center region of the selected portion of the lens as a light transmitting region.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicants: Omnivision Technologies, Inc., VisEra Technologies Company LimitedInventors: Ming-Kai LIU, Tzu-Wei HUANG, Jui-Hung CHANG, Chia-Hui HUANG, Teng-Sheng CHEN
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Publication number: 20130292830Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20130292831Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Kai Liu, Shih-Wei Liang, Hsien-Wei Chen, Kai-Chiang Wu
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Patent number: 8557626Abstract: Disclosed is a method for forming an image sensor device. First, a lens is provided, and a first sacrificial element is then formed on the lens. Subsequently, an electromagnetic interference layer is formed on the lens and the first sacrificial element, and the first sacrificial element and the electromagnetic interference layer thereon are removed to form an electromagnetic interference pattern having an opening exposing a selected portion of the lens. A second sacrificial element is formed in the opening to cover a center region of the selected portion of the lens, while a peripheral region of the selected portion of the lens remains exposed. Next, a light-shielding layer is formed on the electromagnetic interference pattern, the second sacrificial element, and the peripheral region of the selected portion of the lens. Thereafter, the second sacrificial element and the light-shielding pattern thereon are removed to expose the center region of the selected portion of the lens as a light transmitting region.Type: GrantFiled: June 4, 2010Date of Patent: October 15, 2013Assignees: Omnivision Technologies, Inc., VisEra Technologies Company LimitedInventors: Ming-Kai Liu, Tzu-Wei Huang, Jui-Hung Chang, Chia-Hui Huang, Teng-Sheng Chen
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Publication number: 20110298073Abstract: Disclosed is a method for forming an image sensor device. First, a lens is provided, and a first sacrificial element is then formed on the lens. Subsequently, an electromagnetic interference layer is formed on the lens and the first sacrificial element, and the first sacrificial element and the electromagnetic interference layer thereon are removed to form an electromagnetic interference pattern having an opening exposing a selected portion of the lens. A second sacrificial element is formed in the opening to cover a center region of the selected portion of the lens, while a peripheral region of the selected portion of the lens remains exposed. Next, a light-shielding layer is formed on the electromagnetic interference pattern, the second sacrificial element, and the peripheral region of the selected portion of the lens. Thereafter, the second sacrificial element and the light-shielding pattern thereon are removed to expose the center region of the selected portion of the lens as a light transmitting region.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Inventors: Ming-Kai Liu, Tzu-Wei Huang, Jui-Hung Chang, Chia-Hui Huang, Teng-Sheng Chen