Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

Abstract: A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.

Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: The present disclosure generally relates to isolation of a semiconductor device formed in a semiconductor substrate. In an example, a semiconductor device includes a drift well, a drain region, a first dopant isolation region, and a second dopant isolation region. The drift well, drain region, first dopant isolation region, and second dopant isolation region are disposed in a semiconductor substrate. The drift well, drain region, and second dopant isolation region are doped with a first dopant conductivity type. The first dopant isolation region is doped with a second dopant conductivity type opposite from the first dopant conductivity type. The drain region is disposed within the drift well. The first dopant isolation region circumscribes the drain region. The first dopant isolation region is an electrically floating node. The second dopant isolation region circumscribes the first dopant isolation region.

Abstract: The present disclosure introduces a microelectronic device including a source side field plate in a microelectronic device. The microelectronic device may be configured as a metal oxide semiconductor (MOS) transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a CMOS transistor, or a gated bipolar device. The source side field plate extends over the source region by a distance which is more than a quarter of the width of the source region. Transistors may suffer from Vt shifts during gate and drain stress over time. The source side field plate reduces the electric field of the transistor near the gate electrode corner on the source side of the transistor. The gate injection current on the source side and electron trapping in the gate oxide thereby reduced which reduces Vt shifts over time.

Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: An integrated circuit including a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a body region. The source region includes an outer region having a first conductivity type complementary to a second conductivity type of an outer region of the body and an interior-positioned conductive region having the second conductivity type.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: One example includes an integrated circuit (IC) comprising a fin field effect transistor (FinFET). The FinFET includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a drift region adjacent the drain region. The fin also includes a field-plating (FP) dielectric layer on a first side, a second side, and a third side of the drift region. The FP dielectric layer includes a high-K material.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: A method of fabricating an integrated circuit includes forming and patterning a hardmask over a substrate such that the patterned hardmask exposes regions of the substrate. The exposed regions are etched, thereby forming trenches and a semiconductor fin between the trenches. Prior to removing the hardmask, a photoresist layer is formed and patterned, thereby exposing a section of the semiconductor fin. A dopant is implanted into the exposed section through the hardmask.

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

Abstract: An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.