Patents by Inventor Ming-Yih Wang

Ming-Yih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707179
    Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
  • Publication number: 20200168729
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventors: CHIN-SHAN WANG, YI-MIAW LIN, MING-YIH WANG
  • Publication number: 20200104456
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a difference in capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
    Type: Application
    Filed: January 11, 2019
    Publication date: April 2, 2020
    Inventors: HSUAN-MING HUANG, AN SHUN TENG, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
  • Patent number: 9780106
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Publication number: 20150102397
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Patent number: 8947938
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Publication number: 20140085984
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Patent number: 7428108
    Abstract: An optical zoom lens module including a base, a first lens holder, a first tracking controller, a first lens, a second lens holder, a second tracking controller, and a second lens is provided. The base has a main shaft, a secondary shaft, and an opening. The first and second lens holders having a first and a second fixing portion disposed to the secondary shaft are disposed on the base. The first and second tracking controllers covering each other and connected to the first and the second lens holders cover the main shaft. The first lens is disposed on the first lens holder and above the opening. The second lens is disposed on the second lens holder and between the first lens and the opening. The first and second tracking controllers are suitable for moving along the main shaft to adjust the relative distance between the first and the second lens.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 23, 2008
    Assignee: ASUSTeK Computer Inc.
    Inventor: Ming-Yih Wang
  • Publication number: 20080013189
    Abstract: An optical zoom lens module including a base, a first lens holder, a first tracking controller, a first lens, a second lens holder, a second tracking controller, and a second lens is provided. The base has a main shaft, a secondary shaft, and an opening. The first and second lens holders having a first and a second fixing portion disposed to the secondary shaft are disposed on the base. The first and second tracking controllers covering each other and connected to the first and the second lens holders cover the main shaft. The first lens is disposed on the first lens holder and above the opening. The second lens is disposed on the second lens holder and between the first lens and the opening. The first and second tracking controllers are suitable for moving along the main shaft to adjust the relative distance between the first and the second lens.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 17, 2008
    Applicant: ASUSTEK COMPUTER INC.
    Inventor: Ming-Yih Wang