Abstract: Apparatuses, systems, and methods for using defrag levels to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include setting a first defrag level for a memory device, determining if a buffer is full while performing defrag operations on the memory device according to the first defrag level, setting a second defrag level for the memory device in response to determining the buffer is full while performing defrag operations according to the first defrag level.

Abstract: A redundant multiport memory for vehicle applications can have different ports coupled to different hosts that are configured to provide advanced driver assistance system (ADAS) for the vehicle. Different multiport memory devices can provide primary or secondary storage of data for the hosts. At least one of the hosts can perform a functionality check on at least one of the multiport memory devices and make use of a second multiport memory device to which it is coupled if a first multiport memory device to which it is coupled fails the check.

Abstract: An engineering facility scheduling method provided by the present application includes: obtaining facility information and working condition information of an engineering facility; obtaining, based on the facility information, a scheduling group where the engineering facility is located, and obtaining a scheduling policy corresponding to the scheduling group; generating, based on the scheduling policy and the working condition information of the engineering facility, a scheduling instruction for instructing the engineering facility to perform work; and sending the scheduling instruction to the engineering facility. According to the engineering facility scheduling method of the present application, the scheduling instruction can be generated according to the specific scheduling policy and working condition information, thereby increasing the degree of automation of engineering facility scheduling and improving engineering facility scheduling efficiency.

Abstract: A memory sub-system can allocate a first portion of blocks of a memory device for storage of file system metadata based on a file system and a capacity of the memory device, write video data received from a host within a second portion of the blocks at a first data density, and write file system metadata within the first portion of the blocks at a second data density lesser than the first data density.

Abstract: Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.

Abstract: A redundant multiport memory for vehicle applications can have different ports coupled to different hosts that are configured to provide advanced driver assistance system (ADAS) for the vehicle. Different multiport memory devices can provide primary or secondary storage of data for the hosts. At least one of the hosts can perform a functionality check on at least one of the multiport memory devices and make use of a second multiport memory device to which it is coupled if a first multiport memory device to which it is coupled fails the check.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A system to progressively generate responses configured to mitigate risk associated with row hammer attacks. Between two successive refreshing of memory cells in a memory device, increasing thresholds are used to detect row hammer attacks. For example, after a first alert of row hammer attacks is generated using a first lower threshold, a first operation associated with the first lower threshold is initiated to mitigate risk associated with row hammer attack; and a second higher threshold is used to detect row hammer attacks. After a second alert of row hammer attacks is generated using the second lower threshold, a second operation associated with the second lower threshold is initiated to mitigate risk associated with row hammer attack.

Abstract: A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.

Abstract: A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

Abstract: Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.

Abstract: Methods, systems, and devices for an improved power supply for a memory device are described. An apparatus may include a memory device, one or more voltage detectors, and one or more voltage converters. A voltage detector may generate an output indicating whether a voltage at a first pin of the apparatus satisfies a threshold. A voltage converter may be coupled with the voltage detector and may be configured to selectively output a second voltage depending on the output of the voltage detector. Circuitry within the memory device may be coupled with one or more voltage detectors and one or more voltage converters and configured to select a supply voltage for another component of the memory device from among the first voltage (e.g., received from the first pin) and the second voltage (e.g., selectively generated and output by the voltage converter) based on the output from the voltage detector.

Abstract: Methods, systems, and apparatus related to memory management based on temperature evaluation and a status of storage media availability (e.g., whether usage of the storage media exceeds a threshold). In one approach, the memory management is implemented in a memory device having first and second memories. A controller of the memory device evaluates data from a temperature sensor to determine that a temperature of the memory device exceeds a normal operating range. Based on this evaluation, the controller selects the first memory (e.g., SLC memory) for storing incoming data. If the first memory becomes full, the controller switches to the second memory (e.g., TLC or QLC memory) for storing additional incoming data. When the temperature returns to the normal operating range, the additional data is re-written while in the normal operating range.

Abstract: A production host can learn the production state awareness (PSA) modes supported by a memory device and select a particular of one of the supported PSA modes. The memory device can receive host image data from the production host and write the host image data according to the selected PSA mode. The memory device can set a PSA state to load complete after writing the host image data. The memory device can thereby be better situated for being soldered to a memory sub-system.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A memory sub-system can receive a definition of a performance target for each of a number of applications that use the memory sub-system for storage. The memory sub-system can create a plurality of partitions according to the definitions and assign each of the partitions to a block group. The memory sub-system can operate each block group with a trim tailored to the performance target corresponding to that block group and application.

Abstract: A vehicle memory sub-system can be switched from a normal mode to a pre-shutdown mode and initiate a media management operation before shutting down. The mode switch and/or media management operation can be performed in response to receiving a shutdown or pre-shutdown command for the vehicle. After completion of the memory management operation the vehicle and/or memory sub-system can be shutdown.

Abstract: A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

Abstract: Methods, systems, and devices for an improved power supply for a memory device are described. An apparatus may include a memory device, one or more voltage detectors, and one or more voltage converters. A voltage detector may generate an output indicating whether a voltage at a first pin of the apparatus satisfies a threshold. A voltage converter may be coupled with the voltage detector and may be configured to selectively output a second voltage depending on the output of the voltage detector. Circuitry within the memory device may be coupled with one or more voltage detectors and one or more voltage converters and configured to select a supply voltage for another component of the memory device from among the first voltage (e.g., received from the first pin) and the second voltage (e.g., selectively generated and output by the voltage converter) based on the output from the voltage detector.

Abstract: A memory sub-system can receive a definition of a performance target for each of a number of applications that use the memory sub-system for storage. The memory sub-system can create a plurality of partitions according to the definitions and assign each of the partitions to a block group. The memory sub-system can operate each block group with a trim tailored to the performance target corresponding to that block group and application.