Abstract: A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

Abstract: Methods, systems, and devices for an improved power supply for a memory device are described. An apparatus may include a memory device, one or more voltage detectors, and one or more voltage converters. A voltage detector may generate an output indicating whether a voltage at a first pin of the apparatus satisfies a threshold. A voltage converter may be coupled with the voltage detector and may be configured to selectively output a second voltage depending on the output of the voltage detector. Circuitry within the memory device may be coupled with one or more voltage detectors and one or more voltage converters and configured to select a supply voltage for another component of the memory device from among the first voltage (e.g., received from the first pin) and the second voltage (e.g., selectively generated and output by the voltage converter) based on the output from the voltage detector.

Abstract: A memory sub-system can receive a definition of a performance target for each of a number of applications that use the memory sub-system for storage. The memory sub-system can create a plurality of partitions according to the definitions and assign each of the partitions to a block group. The memory sub-system can operate each block group with a trim tailored to the performance target corresponding to that block group and application.

Abstract: A memory sub-system can allocate a first portion of blocks of a memory device for storage of file system metadata based on a file system and a capacity of the memory device, write video data received from a host within a second portion of the blocks at a first data density, and write file system metadata within the first portion of the blocks at a second data density lesser than the first data density.

Abstract: A vehicle memory sub-system can be switched from a normal mode to a pre-shutdown mode and initiate a media management operation before shutting down. The mode switch and/or media management operation can be performed in response to receiving a shutdown or pre-shutdown command for the vehicle. After completion of the memory management operation the vehicle and/or memory sub-system can be shutdown.

Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

Abstract: Methods, systems, and devices for triggering a refresh for non-volatile memory are described. A host system may communicate with a memory system, where the host system and memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down and may enter a power off state in response to the indication. The host system may detect a trigger (e.g., using a time or temperature input) to switch back to a power on state while the vehicle is powered down, the trigger associated with performing a refresh operation at the memory system. The host system may enter the power on state and may transmit a power on command to the memory system. The memory system may perform the refresh operation on one or more memory cells while the vehicle remains in the powered down state.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: Methods, systems, and apparatus related to memory management based on temperature evaluation and a status of storage media availability (e.g., whether usage of the storage media exceeds a threshold). In one approach, the memory management is implemented in a memory device having first and second memories. A controller of the memory device evaluates data from a temperature sensor to determine that a temperature of the memory device exceeds a normal operating range. Based on this evaluation, the controller selects the first memory (e.g., SLC memory) for storing incoming data. If the first memory becomes full, the controller switches to the second memory (e.g., TLC or QLC memory) for storing additional incoming data. When the temperature returns to the normal operating range, the additional data is re-written while in the normal operating range.

Abstract: Programming video data to different portions of memory is described herein. An example system includes a host interface, a memory device having a first portion and a second portion, and a controller coupled to the host interface and the memory device. The controller can be configured to program video data received via the host interface to the first portion of the memory device, and program video data received via the host interface to the second portion of the memory device instead of to the first portion of the memory device in response to receiving a signal that a trigger event has occurred.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.