Patents by Inventor Mitsuru Sato
Mitsuru Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180032272Abstract: An information processing device includes a main memory including a non-volatile memory and a volatile memory with access speed higher than the non-volatile memory, the volatile memory storing data in the non-volatile memory, a processor that issues a read request, a write request and a snapshot request and a memory controller that reads, in response to the read request, data in the volatile memory, writes, in response to the write request, write data in the volatile memory and also writes a write history in a sequential manner to the non-volatile memory, performs, in response to the snapshot request, snapshot processing of recording in non-volatile memory a write position of the write history up to a time of a snapshot, and performs, after the snapshot processing, data restoration processing of writing the written data at the write position in the write history to the non-volatile memory.Type: ApplicationFiled: June 8, 2017Publication date: February 1, 2018Applicant: FUJITSU LIMITEDInventor: Mitsuru SATO
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Patent number: 9842853Abstract: A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.Type: GrantFiled: December 16, 2015Date of Patent: December 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mitsuru Sato, Shigeki Kobayashi, Tsutomu Murase
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Publication number: 20170351972Abstract: A learning model difference providing method that causes a computer to execute a process which includes: calculating a mismatch degree between prediction data about arbitrary data included in a plurality of pieces of data that are input by using an application program, the prediction data being obtained by the plurality of pieces of data and a learning model in accordance with a purpose of use of the application program, and data that are specified for the arbitrary data; assessing whether or not the calculated mismatch degree exceeds a first degree; and transmitting the mismatch degree to a providing source of the learning model in a case where the mismatch degree is assessed as exceeding the first degree.Type: ApplicationFiled: April 27, 2017Publication date: December 7, 2017Applicant: FUJITSU LIMITEDInventors: Tomo Kaniwa, Mitsuru Sato
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Publication number: 20170338244Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: August 2, 2017Publication date: November 23, 2017Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 9764871Abstract: A blood-sampling-tube automatic preparation device comprising a blood-sampling-tube containing section having at least two blood-sampling-tube containers, a label printing and pasting unit that prints blood sampling information data and then pastes the printed label on a surface of a blood-sampling-tube, a hand pasting label printer, a blood-sampling-tube collecting section in which one or more blood-sampling-tubes with label pasted and/or one or more printed labels for hand pasting are collected for each patient, a blood-sampling-tube transferring device that receives a blood-sampling-tube from the blood-sampling-tube container and transfers it to the label printing and pasting unit, and a control device that controls each component.Type: GrantFiled: July 17, 2013Date of Patent: September 19, 2017Assignee: TECHNO-MEDICA CO., LTD.Inventor: Mitsuru Sato
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Patent number: 9748337Abstract: Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a semiconductor substrate having a top surface spread in the first and second directions, and a plurality of conductive layers laminated at predetermined intervals in the third direction on the semiconductor substrate. The semiconductor memory device further includes a columnar semiconductor layer having an interface that is in contact with the semiconductor substrate on a side surface. The columnar semiconductor layer is opposed to the plurality of conductive layers. The columnar semiconductor layer has the third direction as a lengthwise direction. The interface exists in a position deeper than the top surface of the semiconductor substrate in the third direction.Type: GrantFiled: September 10, 2015Date of Patent: August 29, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shigeki Kobayashi, Mitsuru Sato, Tomohiro Yamada
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Patent number: 9748260Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 29, 2015Date of Patent: August 29, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20170134596Abstract: Provided is an information processing apparatus including a receiving unit that receives an operation for an operation target device, and an acquisition unit that acquires, through a near field radio communication, information on the operation target device, which is stored in the operation target device connected through the near field radio communication, during the operation, wherein the information on the operation target device is information that the operation target device acquires from an external device.Type: ApplicationFiled: April 7, 2016Publication date: May 11, 2017Applicant: FUJI XEROX CO., LTD.Inventors: Mitsuru SATO, Masaya KOJIMA, Hideo SASAGAWA, Kazuya IIMURA, Kiyoshi TAKAHASHI, Hiroyuki TOJO
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Patent number: 9598197Abstract: Provided is a double-decker tube dispenser that is not only compact but also highly portable, can be set easily on a cart, a desk, and the like, is capable of responding immediately in case of emergency such as disaster, and enables blood sampling tubes of different types to be prepared in response to blood sampling instructions from doctors. A blood sampling tube stocker device is arranged in an overlapping manner above a printing-and-pasting device, and hence a horizontal width can be extremely reduced. With this, the double-decker tube dispenser, which is not only significantly compact but also highly portable, and applicable not only to medium and small hospitals and hospital wards for inpatients, but also, for example, to facilities specializing in blood sampling, and enables use beside a sickbed, desktop use, and use on a mobile cart and the like in a state in which the dispenser is simply mounted thereon, is provided.Type: GrantFiled: July 9, 2013Date of Patent: March 21, 2017Assignee: TECHNOMEDICA CO., LTD.Inventor: Mitsuru Sato
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Publication number: 20170077121Abstract: A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.Type: ApplicationFiled: December 16, 2015Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuru SATO, Shigeki Kobayashi, Tsutomu Murase
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Publication number: 20170025435Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a select gate; a first insulating film; and a semiconductor film provided in the stacked body and in the substrate. The select gate includes a first portion provided on the substrate and spreading on a first plane crossing a stacking direction of the stacked body, and a second portion provided in the substrate and provided integrally with the first portion. The first insulating film is provided between the select gate and the substrate.Type: ApplicationFiled: February 8, 2016Publication date: January 26, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuru SATO
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Publication number: 20170003494Abstract: According to an illustrative embodiment an imaging system is provided. The system includes a lens tube; a first polarizing filter; and a second polarizing filter; wherein the first polarizing filter and the second polarizing filter are adjacent each other, and wherein a polarizing imparted by the first polarizing filter is different from a polarizing imparted by the second polarizing filter.Type: ApplicationFiled: August 8, 2016Publication date: January 5, 2017Applicant: Sony CorporationInventors: Hiroshi Kosugi, Shuzo Sato, Eiji Otani, Mitsuru Sato
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Publication number: 20160378900Abstract: A non-transitory computer-readable storage medium storing a circuit design support program that causes a computer to execute a process including generating topology data indicating wiring states of components in a circuit to be designed based on circuit data, the topology data including at least one coupling line between each pair of nodes including at least one first node and at least one second node, each of the at least one first node corresponding to each of the components and each of the at least one second node corresponding to each of at least one branch point in a wiring of the circuit when the wiring includes the at least one branch point, and displaying the generated topology data and an input field for receiving an input of restrictive data indicating restrictive requirements for each of the at least one coupling line between each of the nodes.Type: ApplicationFiled: June 20, 2016Publication date: December 29, 2016Applicant: FUJITSU LIMITEDInventors: Ryoko OKUBO, Mitsuru Sato, Kazunori Kumagai
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Patent number: 9466667Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers separately stacked each other; a plurality of columnar sections provided in the stacked body and extending in a stacking direction of the stacked body; and a first insulating section separating the stacked body. The respective columnar sections include a semiconductor body extending in the stacking direction; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The first insulating section includes a first air gap.Type: GrantFiled: March 6, 2015Date of Patent: October 11, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Soichirou Kitazaki, Mitsuru Sato, Megumi Ishiduki
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Publication number: 20160292108Abstract: An information processing device includes an input and output unit to which an input/output device is able to be connected, an information holding unit that registers identification information of a monitoring target input/output device which is not compatible with an error suppression function of suppressing propagation of errors occurring when the input/output device is disconnected from the input and output unit, an execution unit that executes an individual program using infrastructure software, and a determining unit that, by executing the infrastructure software and the individual program, when an access to a first area of the monitoring target input/output device is detected, detects that a value read from a second area of the monitoring target input/output device is an abnormal value as a result of determining whether the value read from the second area is a predetermined value.Type: ApplicationFiled: March 15, 2016Publication date: October 6, 2016Applicant: FUJITSU LIMITEDInventors: Yotaro Konishi, Mitsuru SATO
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Publication number: 20160268268Abstract: Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a semiconductor substrate having a top surface spread in the first and second directions, and a plurality of conductive layers laminated at predetermined intervals in the third direction on the semiconductor substrate. The semiconductor memory device further includes a columnar semiconductor layer having an interface that is in contact with the semiconductor substrate on a side surface. The columnar semiconductor layer is opposed to the plurality of conductive layers. The columnar semiconductor layer has the third direction as a lengthwise direction. The interface exists in a position deeper than the top surface of the semiconductor substrate in the third direction.Type: ApplicationFiled: September 10, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki KOBAYASHI, Mitsuru Sato, Tomohiro Yamada
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Patent number: 9373634Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.Type: GrantFiled: May 8, 2015Date of Patent: June 21, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Sato, Masaru Kito, Megumi Ishiduki, Ryota Katsumata
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Publication number: 20160152367Abstract: It is an object of the present invention to provide a blood-sampling-tube automatic preparation device having a quite short width and a superior portability, and being very compact.Type: ApplicationFiled: July 17, 2013Publication date: June 2, 2016Inventor: Mitsuru SATO
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Publication number: 20160078910Abstract: According to one embodiment, a driving method of a semiconductor memory device, the semiconductor memory device has a stacked body, in which a first electrode film, a second electrode film, a third electrode film are stacked in this order via insulating films, a first semiconductor pillar extending in a stacking direction of the first electrode film, the second electrode film, and the third electrode film and provided in the stacked body, and a memory film. The driving method comprises applying a first voltage to the third electrode film, the first voltage being lower than a second voltage applied to the first electrode film, in case applying a program voltage to the second electrode film, the program voltage to inject charges from the first semiconductor pillar to a portion of the memory film located between the first semiconductor pillar and the second electrode film.Type: ApplicationFiled: March 13, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuru SATO
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Publication number: 20160071926Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers separately stacked each other; a plurality of columnar sections provided in the stacked body and extending in a stacking direction of the stacked body; and a first insulating section separating the stacked body. The respective columnar sections include a semiconductor body extending in the stacking direction; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The first insulating section includes a first air gap.Type: ApplicationFiled: March 6, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Soichirou KITAZAKI, Mitsuru Sato, Megumi Ishiduki